GWIXP425BBT datasheet(27/134 Pages) INTEL

27 / 134 page

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

Datasheet

March 2005

Document Number: 252479, Revision: 005

• Eight-entry write buffer allows the core to continue execution while data is written to memory

• Multiple-accumulate coprocessor that can do two simultaneous, 16-bit, SIMD multiplies with

40-bit accumulation for efficient, high-quality media and signal processing

• Performance monitoring unit (PMU) furnishing two 32-bit event counters and one 32-bit cycle

counter for analysis of hit rates, etc.

This PMU is for the Intel XScale core only. An additional PMU is supplied for monitoring of

internal bus performance.

• JTAG debug unit that uses hardware break points and 256-entry trace history buffer (for flow-

change messages) to debug programs

2.2.1

Super Pipeline

The super pipeline is composed of integer, multiply-accumulate (MAC), and memory pipes.

The integer pipe has seven stages:

• Branch Target Buffer (BTB)/Fetch 1

• Fetch 2

• Decode

• Register File/Shift

• ALU Execute

• State Execute

• Integer Writeback

Figure 6.

Intel XScale® Core Block Diagram

A9568-02

Multiply

Accumulate

Execution

Core

Interrupt

Request

Instruction

FIQ

Coprocessor Interface

IRQ

Data

Address

Data

System

Management

Debug/

PMU

JTAG

South

AHB

Bus

Data Cache

32 KB

Mini-Data Cache

2 KB

Instruction Cache

32 KB

Branch Target Cache

GWIXP425BBT 数据表(PDF) 27 Page - Intel Corporation

GWIXP425BBT 数据表(HTML) 27 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载