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GWIXC1100BCT 数据表(PDF) 94 Page - Intel Corporation |
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GWIXC1100BCT 数据表(HTML) 94 Page - Intel Corporation |
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94 / 134 page  Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor March 2005 Datasheet 94 Document Number: 252479, Revision: 005 5.5.1.2 PCI Clock Timings 5.5.1.3 MII Clock Timings 5.5.1.4 UTOPIA-2 Clock Timings 5.5.1.5 Expansion Bus Clock Timings Table 41. PCI Clock Timings Symbol Parameter 33 MHz 66 MHz Units Notes Min. Max. Min. Max. TPERIODPCICLK Clock period for PCI Clock 30 15 ns TCLKHIGH PCI Clock high time 11 6 ns TCLKLOW PCI Clock low time 11 6 ns TRISE/FALL Rise and fall time requirements for PCI Clock 22 ns Table 42. MII Clock Timings Symbol Parameter Min. Nom. Max. Units Notes Tperiod100Mbit Clock period for Tx and Rx Ethernet clocks 25 25 MHz Tperiod10Mbit Clock period for Tx and Rx Ethernet clocks 2.5 2.5 MHz Tduty Duty cycle for Tx and Rx Ethernet clocks 35 50 65 % Trise/fall Rise and fall time requirements for Tx and Rx Ethernet clocks 2ns Table 43. UTOPIA-2 Clock Timings Symbol Parameter Min. Nom. Max. Units Notes Tperiod Clock period for Tx and Rx UTOPIA-2 clocks 33 MHz 1 Tduty Duty cycle for Tx and Rx UTOPIA-2 clocks 40 50 60 % 1 Trise/fall Rise and fall time requirements for Tx and Rx UTOPIA-2 clocks 2ns 1 Note: 1. The UTOPIA interface can operate at a minimum frequency greater than 0 Hz. Table 44. Expansion Bus Clock Timings Symbol Parameter Min. Nom. Max. Units Notes Tperiod Clock period for expansion-bus clock 66 MHz Tduty Duty cycle for expansion-bus clock 40 50 60 % Trise/fall Rise and fall time requirements for expansion-bus clock 2ns |
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