GWIXC1100BCT datasheet(28/134 Pages) INTEL

28 / 134 page

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

March 2005

Datasheet

Document Number: 252479, Revision: 005

The memory pipe has eight stages:

• The first five stages of the Integer pipe (BTB/Fetch 1 through ALU Execute)

. . . then finish with the following memory stages:

• Data Cache 1

• Data Cache 2

• Data Cache Writeback

The MAC pipe has six to nine stages:

• The first four stages of the Integer pipe (BTB/Fetch 1 through Register File/ Shift)

. . . then finish with the following MAC stages:

• MAC 1

• MAC 2

• MAC 3

• MAC 4

• Data Cache Writeback

The MAC pipe supports a data-dependent early terminate where stages MAC 2, MAC 3, and/or

MAC 4 are bypassed.

Deep pipes promote high instruction execution rates only when a means exists to successfully

predict the outcome of branch instructions. The branch target buffer provides such a means.

2.2.2

Branch Target Buffer (BTB)

Each entry of the 128-entry BTB contains the address of a branch instruction, the target address

associated with the branch instruction, and a previous history of the branch being taken or not

taken. The history is recorded as one of four states:

The BTB can be enabled or disabled via Coprocessor 15, Register 1.

When the address of the branch instruction hits in the BTB and its history is strongly or weakly

taken, the instruction at the branch target address is fetched. When its history is strongly or weakly

not-taken, the next sequential instruction is fetched. In either case the history is updated.

Data associated with a branch instruction enters the BTB the first time the branch is taken. This

data enters the BTB in a slot with a history of strongly not-taken (overwriting previous data when

present).

Successfully predicted branches avoid any branch-latency penalties in the super pipeline.

Unsuccessfully predicted branches result in a four to five cycle branch-latency penalty in the super

pipeline.

• Strongly taken

• Weakly taken

• Weakly not taken

• Strongly not taken

GWIXC1100BCT 数据表(PDF) 28 Page - Intel Corporation

GWIXC1100BCT 数据表(HTML) 28 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载