数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

GWIXC1100BCT 数据表(PDF) 116 Page - Intel Corporation

部件名 GWIXC1100BCT
功能描述  Intel짰 IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
PDF  134 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

GWIXC1100BCT 数据表(HTML) 116 Page - Intel Corporation

Back Button GWIXC1100BCT Datasheet HTML 112Page - Intel Corporation GWIXC1100BCT Datasheet HTML 113Page - Intel Corporation GWIXC1100BCT Datasheet HTML 114Page - Intel Corporation GWIXC1100BCT Datasheet HTML 115Page - Intel Corporation GWIXC1100BCT Datasheet HTML 116Page - Intel Corporation GWIXC1100BCT Datasheet HTML 117Page - Intel Corporation GWIXC1100BCT Datasheet HTML 118Page - Intel Corporation GWIXC1100BCT Datasheet HTML 119Page - Intel Corporation GWIXC1100BCT Datasheet HTML 120Page - Intel Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 116 / 134 page
background image
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
March 2005
Datasheet
116
Document Number: 252479, Revision: 005
Tdata_setup
Data valid prior to the rising edge of the HDS1 data
strobe.
4
5
Cycles
3, 5, 6
Tdata_hold
Data valid after the rising edge of the HDS1 data strobe.
4
36
Cycles
3, 6
Trecov
Time required between successive accesses on the
expansion interface.
2
17
Cycles
4, 6
Table 59.
HPI-8 Mode Write Access Values
Symbol
Parameter
Min.
Max.
Units
Notes
Notes:
1.
The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T
clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the
Intel® IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to
recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is de-
active.
2.
The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T
clocks for setup phase.
3.
The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T
clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel®
IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to
recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de-
active.
4.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the Expansion Bus interface.
5.
HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or
T3 until HRDY is de-active.
6.
One cycle is the period of the Expansion Bus clock.
7.
Timing tests were performed with a 70-pF capacitor to ground.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com