LXT971ABC datasheet(28/90 Pages) INTEL

部件名	LXT971ABC

功能描述	3.3V Dual-Speed Fast Ethernet PHY Transceiver

PDF	90 Pages

Scroll/Zoom	100%

制造商	INTEL [Intel Corporation]

网页	http://www.intel.com

标志

28 / 90 page

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

3.4.3

Reduced Power Modes

The LXT971A offers two power-down modes and a sleep mode.

3.4.3.1

Hardware Power Down

The hardware power-down mode is controlled by the PWRDWN pin. When PWRDWN is High,

the following conditions are true:

• The LXT971A network port and clock are shut down.

• All outputs are three-stated.

• All weak pad pull-up and pull-down resistors are disabled.

• The MDIO registers are not accessible.

Figure 7. Initialization Sequence

MDDIS Voltage

Level?

High

Low

MDIO Control

Mode

Hardware Control

Mode

Disable MDIO Read and

Write Operations

Reset MDIO Registers to

values read at H/W

Control Interface at last

Hardware Reset

MDIO Controlled Operation

(MDIO Writes Enabled)

Power-up or Reset

Initialize MDIO Registers

Read H/W Control

Interface

Software

Reset?

Yes

LXT971ABC 数据表(PDF) 28 Page - Intel Corporation

LXT971ABC 数据表(HTML) 28 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

数据表下载