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MP8861 数据表(PDF) 31 Page - Monolithic Power Systems

部件名 MP8861
功能描述  2.85V - 18V, 6A, High-Efficiency, Wide-Input,Synchronous, Step-Down Converter with Integrated Telemetry via I2C Interface
PDF  37 Pages
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制造商  MPS [Monolithic Power Systems]
网页  http://www.monolithicpower.com
标志 MPS - Monolithic Power Systems

MP8861 数据表(HTML) 31 Page - Monolithic Power Systems

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MP8861 – 2.85V - 18V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER
MP8861 Rev. 1.1
www.MonolithicPower.com
31
5/28/2020
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
Figure 13: Optional External Bootstrap Diode to
Enhance Efficiency
The recommended external BST diode is
IN4148, and the recommended BST capacitor
value is 0.1μF to 1μF.
Connect VCC to VIN at a Low Input Voltage
VCC can be connected to VIN directly when
VIN is lower than 3.5V. This helps improve the
MP8861’s
low
input
voltage
efficiency
performance. To use this application set-up, the
VIN spike voltage must be limited below 4V;
otherwise, VCC may be damaged.
PCB Layout Guidelines (9)
Efficient PCB layout is critical for stable
operation. For best results, refer to Figure 14
and follow the guidelines below. A four-layer
layout is strongly recommended to achieve
better thermal performance.
1. Place the high-current paths (PGND, VIN,
and SW) very close to the device with short,
direct, and wide traces.
2. Keep the VIN and PGND pads connected
with large copper planes.
3. Use at least two layers for the VIN and
PGND trace to achieve better thermal
performance.
4. Add several vias close to the VIN and
PGND pads to help with thermal dissipation.
Place m than one via adjacent to the inner
edge of PGND pad which connects to
AGND pad through low impedance routing
or ground plane.
5. Place the input capacitors as close to VIN
and PGND as possible.
6. Place the decoupling capacitor as close to
VCC and AGND as possible.
7. Add several vias close the the AGND pad,
and connect to PGND plane with Kelvin
connection.
8. Place the external feedback resistors next
to FB.
9. Ensure that there is no via on the FB trace.
10. Keep the switching node SW short and
away from the feedback network.
11. Keep the BST voltage path (BST, C3, and
SW) as short as possible.
NOTE:
9)
The recommended layout is based on the Typical
Application Circuit on page 33-35.



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