MP8861 – 2.85V - 18V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER

MP8861 Rev. 1.1

www.MonolithicPower.com

7

5/28/2020

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I2C PORT SIGNAL CHARACTERISTICS

Parameter

Symbol

Condition

Cb = 100pF

Cb = 400pF

Units

Min

Max

Min

Max

SCLH and SCL clock

frequency

fSCHL

0

3.4

0

0.4

MHz

Set-up time for a

repeated start condition

τSU;STA

160

-

600

-

ns

Hold time (repeated) start

condition

τHD;STA

160

-

600

-

ns

Low period of the SCL

clock

τLOW

160

-

1300

-

ns

High period of the SCL

clock

τHIGH

60

-

600

-

ns

Data set-up time

τSU:DAT

10

-

100

-

ns

Data hold time

τHD;DAT

0

70

0

-

ns

Rise time of SCLH signal

τrCL

10

40

20*0.1Cb

300

ns

Rise time of SCLH signal

after a repeated START

condition and after an

acknowledge bit

τfCL1

10

80

20*0.1Cb

300

ns

Fall time of SCLH signal

τfCL

10

40

20*0.1Cb

300

ns

Rise time of SDAH signal

τfDA

10

80

20*0.1Cb

300

ns

Fall time of SDAH signal

τfDA

10

80

20*0.1Cb

300

ns

Set-up time for stop

condition

τSU;STO

160

-

600

-

ns

Bus free time between a

stop and start condition

τBUF

160

-

1300

-

ns

Data valid time

τVD;DAT

-

16

-

90

ns

Data valid acknowledge

time

τVD;ACK

-

160

-

900

ns

Capacitive load for each

bus line

Cb

SDAH and SCLH line

-

100

-

400

pF

SDAH + SDA line

and SCLH + SCL line

-

400

-

400

pF

Noise margin at the low

level

Ci

For each connected

device

-

0.1VCC

0.1VCC

-

V

Noise margin at the high

level

VnH

For each connected

device

-

0.2VCC

0.2VCC

-

V

NOTE:

VCC is the I2C bus voltage, in the 1.8V to 3.6V range, and used for 1.8V, 2.5V, and 3.3V bus voltages.