Device operation

M34C02-W, M34C02-L, M34C02-R

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3.7

Write Operations

Following a Start condition the bus master sends a Device Select Code with the RW bit

reset to 0. The device acknowledges this, as shown in Figure 8, and waits for an address

byte. The device responds to the address byte with an acknowledge bit, and then waits for

the data byte.

bit” time slot), either at the end of a Byte Write or a Page Write, the internal memory Write

cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write

cycle.

During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and

the device does not respond to any requests.

3.7.1

Byte Write

After the Device Select Code and the address byte, the bus master sends one data byte. If

the addressed location is hardware write-protected, the device replies to the data byte with

NoAck, and the location is not modified. If, instead, the addressed location is not Write-

protected, the device replies with Ack. The bus master terminates the transfer by generating

a Stop condition, as shown in Figure 8.

3.7.2

Page Write

The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided

that they are all located in the same page in the memory: that is, the most significant

memory address bits are the same. If more bytes are sent than will fit up to the end of the

page, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to

become overwritten in an implementation dependent way.

The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the

device if Write Control (WC) is Low. If the addressed location is hardware write-protected,

the device replies to the data byte with NoAck, and the locations are not modified. After each

byte is transferred, the internal byte address counter (the 4 least significant address bits

only) is incremented. The transfer is terminated by the bus master generating a Stop

condition.