RT6310CSLASHCH datasheet(40/54 Pages) RICHTEK

40 / 54 page

RT6310

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

DS6310-04

August 2023

estimated as equation below :

CIN

OUT

ESR

= D I

+ I

−





ESR

OUT

Where R

is the equivalent series resistance of C

and

D =





For ceramic capacitors, the equivalent series resistance

(ESR) is very low, the ripple caused by ESR can be

ignored, and the minimum input capacitance

estimated as equation below :

(

)

IN_MIN

OUT_MAX

CIN_MAX

1 D

= I

−





Where

VIN_MAX = 200mV for typical application (VIN 

7V)

CIN Ripple Current

CIN Ripple Voltage

VCIN



(1-D) x IOUT

D x IOUT

(1-D) x tSW

D x tSW

VESR = D x IOUT x ESR

Figure 14. CIN Ripple Voltage and Ripple Current

In addition, the input capacitor needs to have a very low

ESR and must be rated to handle the worst-case RMS

input current of :

OUT

RMS

OUT_MAX

OUT





−

It is common to use the worse IRMS

≅ IOUT/2 at VIN =

2VOUT for design. Note that ripple current ratings from

capacitor manufacturers are often based on only 2000

hours of life. Therefore, the de-rating of capacitor is

worse

actual

application.

Selecting

higher

temperature rating of capacitor is required for less de-

rating.

Several capacitors may also be paralleled to meet size,

height and thermal requirements in the design. For low

input

voltage

applications,

sufficient

bulk

input

capacitance is needed to minimize transient effects

during output load changes.

Ceramic capacitors are ideal for switching regulator

applications due to its small, robust and very low ESR.

However, care must be taken when these capacitors

are used at the input. A ceramic input capacitor

combined with trace or cable inductance forms a high

quality factor (under damped) tank circuit. If the RT6310

circuit is plugged into a live supply, the input voltage can

ring to twice its nominal value, possibly exceeding the

device's rating. This situation is easily avoided by

placing the low ESR ceramic input capacitor in parallel

with a bulk capacitor with higher ESR to damp the

voltage ringing.

The input capacitor should be placed as close as

possible to the VIN pin, with a low inductance

connection to the PGND of the IC. In addition to a larger

bulk capacitor, a small ceramic capacitors of 0.1

F

should be placed close to the VIN pin. The capacitor

should be 0402 or 0603 in size.

Output Capacitor Selection

The selection of COUT should satisfy the voltage ripple,

the transient loads and to ensure that control loop is

stable. Loop stability can be checked by viewing the

load transient response. The peak-to-peak output ripple,

VOUT, is characterized by two components, ESR ripple

VP− P_ESR and capacitive ripple VP−P_C, are

expressed as below :

OUT

P P_ESR

P P_C

= V

+ V

−−



P P_ESR

ESR

= I

−



 

P P_C

OUT

8 C

−





Where the

IL is the peak-to-peak inductor ripple

current and RESR is the equivalent series resistance of

COUT.

The output ripple is highest at maximum input voltage

since

IL increases with input voltage. Multiple

capacitors placed in parallel may be needed to meet the

ESR and RMS current handling requirements.

Regarding to the transient loads, the VSAG and VSOAR

requirement should be taken into consideration for

choosing the output capacitance value. The amount of

output sag is a function of the maximum duty factor,

which is calculated from the on-time and minimum off-

time.

RT6310C/CH 数据表(PDF) 40 Page - Richtek Technology Corporation

RT6310C/CH 数据表(HTML) 40 Page - Richtek Technology Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

数据表下载