VCTA25201B-R33MS6 datasheet(4/50 Pages) RICHTEK

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RTQ2134-QA

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

DSQ2134-QA-02

May

2022

Pin No.

Pin Name

Pin Function

WDOG_RST

Control input for output voltage reset. Reset each Buck output voltage, DVSx,

and ENDVSx registers to factory default setting value when this pin is pulled

low. Connect this pin to be higher than 70% of VIO pin voltage if this pin is not

used. "Do Not" leave this pin floating. The minimum watchdog debounce time

is 100

s.

Note that the factory default setting value in watchdog register (0x25) is 0x00h

(Disabled).

PVIN3

Power input for power stage 3. It is recommended to use a 10-

F, X7R

capacitor.

LX3

Switching node for power stage 3.

LX2

Switching node for power stage 2.

PVIN2

Power input for power stage 2. It is recommended to use a 10-

F, X7R

capacitor.

SCL

Clock input for I2C interface. The pull-up voltage supply must be the same as

VIO voltage for correct operation. Connect this pin to AGND if I2C interface is

not used. "Do Not" leave this pin floating.

SDA

Data line for I2C interface. The pull-up voltage supply must be the same as

VIO voltage for correct operation. Connect this pin to AGND if I2C interface is

not used. "Do Not" leave this pin floating.

INT

Interrupt indicator. When INT function is used, set 0x33[6] = 1, 0x34[6] = 1 and

0x35[6] = 1.

VIO

I/O supply voltage for digital communications. Connect this pin to 1.8V for

normal operation. "Do Not" leave this pin floating.

Master chip enable. A logic-high enables the converter; a logic-low forces the

device into shutdown mode. "Do Not" leave this pin floating.

VOUT2

Output voltage sense for Buck2.

RTN2

Remote ground sense for Buck2.

AVIN

Analog input voltage.

31(Exposed PAD) PGND

Exposed pad. The exposed pad is connected to PGND and must be soldered

to a large PCB copper area for maximum power dissipation.

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