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VCTA25201B-R33MS6 数据表(PDF) 23 Page - Richtek Technology Corporation |
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VCTA25201B-R33MS6 数据表(HTML) 23 Page - Richtek Technology Corporation |
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23 / 50 page ![]() RTQ2134-QA Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2134-QA-02 May 2022 www.richtek.com 23 CIN4 CIN1 PVIN4 LX4 PVIN1 LX1 I 2C CVIO CIN2 CIN3 L2 L3 COUT2_0 COUT3_0 COUT3_1 31 PAD 4 3 5 2 1 6 7 11 19 20 18 21 22 17 16 12 10 9 8 15 14 13 27 26 28 29 30 23 24 25 PVIN2 LX2 PGND PVIN3 LX3 COUT2_1 L4 L1 COUT4_1 COUT1_1 COUT4_0 CAVIN COUT1_0 PGND Connect to PGND in second layer with single node. Keep feedback sense trace away from noise trace to reduce coupling. AVIN_FILT capacitor must be placed as close to IC as possible Add vias on exposed pad for thermal dissipation and current carrying capacity Input capacitors must be placed as close to IC VIN-GND as possible Connect to PGND in second layer with single node. VOUT1 VOUT2 Figure 10 . Layout Guideline for 2 + 2 Application |
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