CC2550-RTR1 datasheet(16/55 Pages) TI

16 / 55 page

CC2550

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 16 of 54

each new byte (every 8 clock pulses). The

burst access is either a read or a write access

and must be terminated by setting CSn high.

For register addresses in the range 0x30-

0x3D, the “burst” bit is used to select between

status registers and command strobes (see

below). The status registers can only be read.

Burst read is not available for status registers,

so they must be read one at a time.

10.3

SPI Read

When reading register fields over the SPI

interface while the register fields are updated

by the radio hardware (e.g. MARCSTATE or

TXBYTES), there is a small, but finite,

probability that a single read from the register

is being corrupt. As an example, the probability

of any single read from TXBYTES being

corrupt, assuming the maximum data rate is

used, is approximately 80 ppm. Refer to the

CC2550 Errata Note for more details.

10.4

Command Strobes

Command strobes may be viewed as single

byte instructions to

CC2550. By addressing a

command strobe register, internal sequences

will be started. These commands are used to

disable the crystal oscillator, enable transmit

mode, flush the TX FIFO etc. The 9 command

strobes are listed in Table 23 on page 35.

The command strobe registers are accessed

in the same way as for a register write

operation, but no data is transferred. That is,

only the R/W bit (set to 0), burst access (set to

0) and the six address bits (in the range 0x30

through 0x3D) are written.

When writing command strobes, the status

byte is sent on the SO pin.

A command strobe may be followed by any

other SPI access without pulling CSn high.

After issuing an SRES command strobe the

next command strobe can be issued when the

pin goes low as shown in Figure 8. The

command strobes are executed immediately,

with the exception of the SPWD and the SXOFF

strobes that are executed when CSn goes

high.

Figure 8: SRES command strobe

10.5

FIFO Access

The 64-byte TX FIFO is accessed through the

0x3F address. When the read/write bit is zero,

the TX FIFO is accessed. The TX FIFO is

write-only.

The burst bit is used to determine if FIFO

access is single byte or a burst access. The

single byte access method expects address

with burst bit set to zero and one data byte.

After the data byte a new address is expected;

hence, CSn can remain low. The burst access

method expects one address byte and then

consecutive data bytes until terminating the

access by setting CSn high.

The following header bytes access the FIFO:

•

0x3F: Single byte access to TX FIFO

•

0x7F: Burst access to TX FIFO

When writing to the TX FIFO, the status byte

(see Section 10.1) is output for each new data

byte on SO, as shown in Figure 6. This status

byte can be used to detect TX FIFO underflow

while writing data to the TX FIFO. Note that

the status byte contains the number of bytes

free before writing the byte in progress to the

TX FIFO. When the last byte that fits in the TX

FIFO is transmitted to the SI pin, the status

byte received concurrently on the SO pin will

indicate that one byte is free in the TX FIFO.

The transmit FIFO may be flushed by issuing a

SFTX

command strobe. The FIFO is cleared

when going to the SLEEP state.

10.6

PATABLE Access

The 0x3E address is used to access the

PATABLE

, which is used for selecting PA

power control settings. The SPI expects up to

eight data bytes after receiving the address.

By programming the PATABLE, controlled PA

power ramp-up and ramp-down can be

achieved. See Section 21 on page 28 for

output power programming details.

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