CC2550-RTR1 datasheet(25/55 Pages) TI

25 / 55 page

CC2550

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 25 of 54

the SLEEP state. After the chip gets back to

the IDLE state, the registers will have default

(reset) contents and must be reprogrammed

over the SPI interface.

16.4

Active Mode

The active transmit mode is activated by the

MCU by using the STX command strobe.

The frequency synthesizer must be calibrated

regularly.

CC2550 has one manual calibration

option (using the SCAL strobe), and three

automatic calibration options, controlled by the

MCSM0.FS_AUTOCAL

setting:

•

Calibrate when going from IDLE to TX

(or FSTXON)

•

Calibrate when going from TX to IDLE

•

Calibrate every fourth time when going

from TX to IDLE

The calibration takes a constant number of

XOSC cycles (see Table 18 for timing details).

When TX is active, the chip will remain in the

TX state until the current packet has been

successfully transmitted. Then the state will

change

indicated

the

MCSM1.TXOFF_MODE

setting. The possible

destinations are:

•

IDLE

•

FSTXON: Frequency synthesizer on

and ready at the TX frequency.

Activate TX with STX.

•

TX: Start sending preambles

The SIDLE command strobe can always be

used to force the radio controller to go to the

IDLE state.

16.5

Timing

The radio controller controls most timing in

CC2550, such as synthesizer calibration and

PLL lock. Timing from IDLE to TX is constant,

dependent on the auto calibration setting. The

calibration time is constant 18739 clock

periods. Table 18 shows timing in crystal clock

cycles for key state transitions.

Power on time and XOSC start-up times are

variable, but within the limits stated in Table 6.

Note that in a frequency hopping spread

spectrum or a multi-channel protocol the

calibration time can be reduced from 721 µs to

approximately 150 µs. This is explained in

Section 26.2.

Description

XOSC

periods

26 MHz

crystal

Idle to TX/FSTXON, no calibration

2298

88.4 µs

Idle to TX/FSTXON, with calibration

~21037

809 µs

TX to IDLE, no calibration

0.1 µs

TX to IDLE, including calibration

~18739

721 µs

Manual calibration

~18739

721 µs

Table 18: State transition timing

Data FIFO

The

CC2550 contains a 64 byte FIFO for data

to be transmitted. The SPI interface is used for

writing to the TX FIFO. Section 10.5 contains

details on the SPI FIFO access. The FIFO

controller will detect underflow in the TX FIFO.

When writing to the TX FIFO it is the

responsibility of the MCU to avoid TX FIFO

overflow. A TX FIFO overflow will result in an

error in the TX FIFO content.

The chip status byte that is available on the SO

pin while transferring the SPI address contains

the fill grade of the TX FIFO. Section 10.1 on

page 15 contains more details on this.

The number of bytes in the TX FIFO can also

be read from the TXBYTES.NUM_TXBYTES

status register.

The 4-bit FIFOTHR.FIFO_THR setting is used

to program the FIFO threshold point. Table 19

lists the 16 FIFO_THR settings and the

corresponding thresholds for the TX FIFO.

A flag will assert when the number of bytes in

the FIFO is equal to or higher than the

programmed threshold. The flag is used to

generate the FIFO status signals that can be

viewed on the GDO pins (see Section 24 on

page 30).

CC2550-RTR1 数据表(PDF) 25 Page - Texas Instruments

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