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CAT25C01LITE13 数据表(PDF) 3 Page - Catalyst Semiconductor

部件名 CAT25C01LITE13
功能描述  1K/2K/4K SPI Serial CMOS EEPROM
PDF  15 Pages
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制造商  CATALYST [Catalyst Semiconductor]
网页  http://www.catalyst-semiconductor.com
标志 CATALYST - Catalyst Semiconductor

CAT25C01LITE13 数据表(HTML) 3 Page - Catalyst Semiconductor

  CAT25C01LITE13 Datasheet HTML 1Page - Catalyst Semiconductor CAT25C01LITE13 Datasheet HTML 2Page - Catalyst Semiconductor CAT25C01LITE13 Datasheet HTML 3Page - Catalyst Semiconductor CAT25C01LITE13 Datasheet HTML 4Page - Catalyst Semiconductor CAT25C01LITE13 Datasheet HTML 5Page - Catalyst Semiconductor CAT25C01LITE13 Datasheet HTML 6Page - Catalyst Semiconductor CAT25C01LITE13 Datasheet HTML 7Page - Catalyst Semiconductor CAT25C01LITE13 Datasheet HTML 8Page - Catalyst Semiconductor CAT25C01LITE13 Datasheet HTML 9Page - Catalyst Semiconductor Next Button
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Discontinued
Parts
3
CAT25C01, CAT25C02, CAT25C04
Doc. No. 1105, Rev. B
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25CXX-1.8
CAT25CXX
1.8V-5.5V
2.5V-5.5V
4.5V-5.5V
Test
SYMBOL PARAMETER
Min.
Max. Min.
Max.
Min.
Max.
UNITS
Conditions
tSU
Data Setup Time
50
20
20
ns
tH
Data Hold Time
50
20
20
ns
tWH
SCK High Time
250
75
40
ns
tWL
SCK Low Time
250
75
40
ns
fSCK
Clock Frequency
DC
1
DC
5
DC
10
MHz
tLZ
HOLD to Output Low Z
50
50
50
ns
tRI(1)
Input Rise Time
2
2
2
µs
tFI(1)
Input Fall Time
2
2
2
µs
tHD
HOLD Setup Time
100
40
40
ns
tCD
HOLD Hold Time
100
40
40
ns
tWC(4)
Write Cycle Time
5
5
5
ms
tV
Output Valid from Clock Low
250
75
40
ns
tHO
Output Hold Time
0
0
0
ns
tDIS
Output Disable Time
250
75
75
ns
tHZ
HOLD to Output High Z
150
50
50
ns
tCS
CS High Time
500
100
100
ns
tCSS
CS Setup Time
500
100
100
ns
tCSH
CS Hold Time
500
100
100
ns
tWPS
WP Setup Time
150
50
50
ns
tWPH
WP Hold Time
150
50
50
ns
A.C. CHARACTERISTICS
Power-Up Timing(1)(3)
Symbol
Parameter
Max.
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) AC Test Conditions:
Input Pulse Voltages: 0.3VCC to 0.7VCC
Input rise and fall times:
≤10ns
Input and output reference voltages: 0.5VCC
Output load: current source IOL max/IOH max; CL=50pF
(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
(4) tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
CL = 50pF
(note 2)



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