Discontinued

Parts

4

CAT25C01, CAT25C02, CAT25C04

Doc. No. 1105, Rev. B

© 2005 by Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

FUNCTIONAL DESCRIPTION

The CAT25C01/02/04 supports the SPI bus data

transmission protocol. The synchronous Serial Peripheral

Interface (SPI) helps the CAT25C01/02/04 to interface

directly with many of today’s popular microcontrollers.

The CAT25C01/02/04 contains an 8-bit instruction

register. (The instruction set and the operation codes

are detailed in the instruction set table)

After the device is selected with

CS going low, the first

byte will be received. The part is accessed via the SI pin,

with data being clocked in on the rising edge of SCK.

The first byte contains one of the six op-codes that define

the operation to be performed.

PIN DESCRIPTION

SI: Serial Input

SI is the serial data input pin. This pin is used to input all

opcodes, byte addresses, and data to be written to the

CAT25010/20/40. Input data is latched on the rising

edge of the serial clock for SPI modes (0, 0 & 1, 1).

SO: Serial Output

SO is the serial data output pin. This pin is used to

transfer data out of the CAT25C01/02/04. During a read

cycle, data is shifted out on the falling edge of the serial

clock for SPI modes (0,0 & 1,1).

Instruction

Opcode

Operation

WREN

0000 0110

Enable Write Operations

WRDI

0000 0100

Disable Write Operations

RDSR

0000 0101

Read Status Register

WRSR

0000 0001

Write Status Register

READ

Read Data from Memory

WRITE

Write Data to Memory

INSTRUCTION SET

Figure 1. Sychronous Data Timing

VALID IN

VIL

HI-Z

HI-Z

CS

SCK

SI

SO

tFI

Note: Dashed Line= mode (1, 1) – ––––

Note:

(1) X=0 for CAT25C01, CAT25C02. X=A8 for CAT25C04.