Discontinued

Parts

9

CAT25C01, CAT25C02, CAT25C04

Doc. No. 1105, Rev. B

© 2005 by Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

Figure 9.

HOLD

HOLD

HOLD

HOLD

HOLD Timing

Figure 8. Page Write Instruction Timing

Note: Dashed Line= mode (1, 1) – ––––

*X=0 for CAT25C01, CAT25C02; X=A8 for CAT25C04

Note: Dashed Line= mode (1, 1) – ––––

CS

SCK

HOLD

SO

tCD

tHD

tHD

tCD

tLZ

tHZ

HIGH IMPEDANCE

SK

SI

SO

00

00

00

10

BYTE ADDRESS

Data

Byte 1

012345678

13

14

15 16-23

24-31

Data

Byte 2

Data

Byte 3

Data Byte N

CS

OPCODE

7..1

0

16+(N-1)x8-1..16+(N-1)x8 16+Nx8-1

DATA IN

HIGH IMPEDANCE

A7

A0

X*

Figure 10.

WP

WP

WP

WP

WP Timing

CS

SCK

WP

WP

Note: Dashed Line= mode (1, 1) – ––––

DESIGN CONSIDERATIONS

The CAT25C01/02/04 powers up in a write disable state

and in a low power standby mode. A WREN instruction

must be issued to perform any writes to the device after

power up. Also,on power up

CS should be brought low

to enter a ready state and receive an instruction. After

a successful byte/page write or status register write, the

CAT25C01/02/04 goes into a write disable mode.

CS

must be set high after the proper number of clock cycles

to start an internal write cycle. Access to the array

during an internal write cycle is ignored and program-

ming is continued. On power up, SO is in a high

impedance. If an invalid op code is received, no data will

be shifted into the CAT25C01/02/04, and the serial

output pin (SO) will remain in a high impedance state

until the falling edge of

CS is detected again.

When powering down, the supply should be taken down

to 0V, so that the CAT25C01/02/04 will be reset when

power is ramped back up. If this is not possible, then,

following a brown-out episode, the CAT25C01/02/04

can be reset by refreshing the contents of the Status

Register (See Application Note AN10).