Discontinued

Parts

6

CAT25C01, CAT25C02, CAT25C04

Doc. No. 1105, Rev. B

© 2005 by Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

Figure 2. WREN Instruction Timing

Figure 3. WRDI Instruction Timing

SCK

SI

CS

SO

Note: Dashed Line = mode (1, 1)

00000

11

0

HIGH IMPEDANCE

SCK

SI

CS

SO

00000

10

0

HIGH IMPEDANCE

Note: Dashed Line = mode (1, 1)

STATUS REGISTER

The Status Register indicates the status of the device.

The

RDY (Ready) bit indicates whether the CAT25C01/

02/04 is busy with a write operation. When set to 1 a

write cycle is in progress and when set to 0 the device

indicates it is ready. This bit is read only. The WEL (Write

Enable) bit indicates the status of the write enable latch.

When set to 1, the device is in a Write Enable state and

when set to 0 the device is in a Write Disable state. The

WEL bit can only be set by the WREN instruction and can

be reset by the WRDI instruction.

The BP0 and BP1 (Block Protect) bits indicate which

blocks are currently protected. These bits are set by the

user issuing the WRSR instruction. The user is allowed

to protect quarter of the memory, half of the memory or

the entire memory by setting these bits. Once protected,

the user may only read from the protected portion of the

array. These bits are non-volatile.

The WPEN (Write Protect Enable) is an enable bit for the

WP pin. The WP pin and WPEN bit in the status register

control the programmable hardware write protect fea-

ture. Hardware write protection is enabled when

WP is

low and WPEN bit is set to high. The user cannot write

to the status register, (including the block protect bits

and the WPEN bit) and the block protected sections in

the memory array when the chip is hardware write

protected. Only the sections of the memory array that

are not block protected can be written. Hardware write

protection is disabled when either

WP pin is high or the

WPEN bit is zero.

DEVICE OPERATION

Write Enable and Disable

The CAT25C01/02/04 contains a write enable latch.

This latch must be set before any write operation. The

applied. WREN instruction will enable writes (set the

latch) to the device. WRDI instruction will disable writes

(reset the latch) to the device. Disabling writes will

protect the device against inadvertent writes.

READ Sequence

The part is selected by pulling

CS low. The 8-bit read

instruction is transmitted to the CAT25C01/02/04,

followed by the 8-bit address for CAT25C01/02/04 (for

the CAT25C04, bit 3 of the read data instruction contains

address A8).