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WM8711SEDS/R 数据表(PDF) 37 Page - Wolfson Microelectronics plc

部件名 WM8711SEDS/R
功能描述  Internet Audio DAC with Integrated Headphone Amplifier
PDF  47 Pages
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制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8711SEDS/R 数据表(HTML) 37 Page - Wolfson Microelectronics plc

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Production Data
WM8711 / WM8711L
w
PD Rev 4.3 September 2006
37
REGISTER MAP
The complete register map is shown in Table 24. The detailed description can be found in the
relevant text of the device description. There are 8 registers with 9 bits per register. These can be
controlled using either the 2 wire or 3 wire MPU interface.
REGISTER
B
15
B
14
B
13
B
12
B
11
B
10
B
9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R2 (04h)
0
0
0
0
0
1
0
LRHP
BOTH
LZCEN
LHPVOL
R3 (06h)
0
0
0
0
0
1
1
RLHP
BOTH
RZCEN
RHPVOL
R4 (08h)
0
0
0
0
1
0
0
0
0
0
0
DAC SEL BYPASS
0
0
0
R5 (0Ah)
0
0
0
0
1
0
1
0
0
0
0
0
DAC MU
DEEMPH
0
R6 (0Ch)
0
0
0
0
1
1
0
0
POWER
OFF
CLK
OUTPD
OSCPD
OUTPD
DACPD
1
1
1
R7 (0Eh)
0
0
0
0
1
1
1
0
BCLK
INV
MS
LR SWAP
LRP
IWL
FORMAT
R8 (10h)
0
0
0
1
0
0
0
0
CLK0
DIV2
CLKI
DIV2
SR
BOSR
USB/
NORM
R9 (12h)
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
ACTIVE
R15(1Eh)
0
0
0
1
1
1
1
RESET
ADDRESS
DATA
Table 23 Mapping of Program Registers
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
6:0
LHPVOL
[6:0]
1111001
( 0dB )
Left Channel Headphone Output
Volume Control
1111111 = +6dB
. . 1dB steps down to
0110000 = -73dB
0000000 to 0101111 = MUTE
7
LZCEN
0
Left Channel Zero Cross detect Enable
1 = Enable
0 = Disable
0000010
Left Headphone
Out
8
LRHPBOTH
0
Left to Right Channel Headphone
Volume, Mute and Zero Cross Data
Load Control
1 = Enable Simultaneous Load of
LHPVOL[6:0] and LZCEN to
RHPVOL[6:0] and RZCEN
0 = Disable Simultaneous Load



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