WM8711SEDSSLASHR datasheet(28/47 Pages) WOLFSON

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Production Data

WM8711 / WM8711L

PD Rev 4.3 September 2006

To accommodate system timing requirements the interpretation of BCLK maybe inverted, this is

controlled via the software shown in Table 9. This is especially appropriate for DSP mode.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

1:0

FORMAT[1:0]

Audio Data Format Select

11 = DSP Mode, frame sync + 2 data

packed words

10 = I

2S Format, MSB-First left-1

justified

01 = MSB-First, left justified

00 = MSB-First, right justified

3:2

IWL[1:0]

Input Audio Data Bit Length Select

11 = 32 bits

10 = 24 bits

01 = 20 bits

00 = 16 bits

LRP

DACLRC phase control (in left, right

or I

2S modes)

1 = Right Channel DAC data when

DACLRC high

0 = Right Channel DAC data when

DACLRC low

(opposite phasing in I

2S mode)

DSP mode A/B select ( in DSP mode

only)

1 = MSB is available on 2

nd BCLK

rising edge after DACLRC rising

edge

0 = MSB is available on 1st BCLK

rising edge after DACLRC rising

edge

LRSWAP

DAC Left Right Clock Swap

1 = Right Channel DAC Data Left

0 = Right Channel DAC Data Right

Master Slave Mode Control

1 = Enable Master Mode

0 = Enable Slave Mode

0000111

Digital Audio

Interface Format

BCLKINV

Bit Clock Invert

1 = Invert BCLK

0 = Don’t invert BCLK

Table 9 Digital Audio Interface Control

Note: If right justified 32 bit mode is selected then the WM8711/L defaults to 24 bits.

WM8711SEDS/R 数据表(PDF) 28 Page - Wolfson Microelectronics plc

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