WM8711SEDSSLASHR datasheet(13/47 Pages) WOLFSON

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Production Data

WM8711 / WM8711L

PD Rev 4.3 September 2006

MASTER CLOCK TIMING

MCLK

XTIL

XTIH

XTIY

Figure 1 System Clock Timing Requirements

Test Conditions

AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25

oC, Slave Mode fs = 48kHz, MCLK = 256fs

unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK System clock pulse width

high

tXTIH

MCLK System clock pulse width

low

tXTIL

MCLK System clock cycle time

tXTIY

MCLK Duty cycle

40:60

60:40

DIGITAL AUDIO INTERFACE – MASTER MODE

BCLK

(Output)

DACLRC

(Output)

DACDAT

DLT

DHT

Figure 2 Digital Audio Data Timing - Master Mode

Test Conditions

AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25

oC, Slave Mode, fs = 48kHz, XTI/MCLK =

256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

DACLRC propagation delay

from BCLK falling edge

tDL

DACDAT setup time to

BCLCK rising edge

tDST

DACDAT hold time from

BCLK rising edge

tDHT

WM8711SEDS/R 数据表(PDF) 13 Page - Wolfson Microelectronics plc

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