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WM8711SEDS/R 数据表(PDF) 14 Page - Wolfson Microelectronics plc |
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WM8711SEDS/R 数据表(HTML) 14 Page - Wolfson Microelectronics plc |
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14 / 47 page  Production Data WM8711 / WM8711L w PD Rev 4.3 September 2006 14 DIGITAL AUDIO INTERFACE – SLAVE MODE BCLK (Input) DACLRC (Input) t BCH t BCL t BCY DACDAT t LRSU t DS t LRH Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25 oC, slave mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns DACLRC set-up time to BCLK rising edge tLRSU 10 ns DACLRC hold time from BCLK rising edge tLRH 10 ns DACDAT set-up time to BCLK rising edge tDS 10 ns DACDAT hold time from BCLK rising edge tDH 10 ns MPU INTERFACE TIMING CSB SCLK SDIN t CSL t DHO t DSU t CSH t SCY t SCH t SCL t SCS LSB t CSS Figure 4 Program Register Input Timing - 3-Wire MPU interface Timing |
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