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WM8955BLGECO/V 数据表(PDF) 35 Page - Wolfson Microelectronics plc |
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WM8955BLGECO/V 数据表(HTML) 35 Page - Wolfson Microelectronics plc |
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35 / 44 page ![]() Production Data WM8955BL w PD Rev 4.1 February 2007 35 POWER MANAGEMENT The WM8955BL has two control registers that allow users to select which functions are active. For minimum power consumption, unused functions should be disabled. To avoid any pop or click noise, it is important to enable or disable functions in the correct order (see Applications Information) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 8:7 VMIDSEL 00 VMID resistor divider select 00 – VMID disabled 01 – 50k Ω divider enabled 10 – 500k Ω divider enabled 11 – 5k Ω divider enabled (for fast start-up) R25 (19h) Power Manageme nt (1) 6 VREF 0 VREF (necessary for all other functions) 8 DACL 0 DAC Left Enable 0=off 1=on 7 DACR 0 DAC Right Enable 0=off 1=on 6 LOUT1 0 LOUT1 Output Buffer* Enable 0=off 1=on 5 ROUT1 0 ROUT1 Output Buffer* Enable 0=off 1=on 4 LOUT2 0 LOUT2 Output Buffer* Enable 0=off 1=on 3 ROUT2 0 ROUT2 Output Buffer* Enable 0=off 1=on 2 MOUT 0 MONOOUT Output Buffer and Mono Mixer Enable 0=off 1=on R26 (1Ah) Power Manageme nt (2) 1 OUT3 0 OUT3 Output Buffer Enable 0=off 1=on Note: * The left mixer is enabled when LOUT1=1 or LOUT2=1. The right mixer is enabled when ROUT1=1 or ROUT2=1. Table 26 Power Management |
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