WM8955BLGECOSLASHV datasheet(29/44 Pages) WOLFSON

部件名	WM8955BLGECO/V

功能描述	Stereo DAC For Portable Audio Applications

PDF	44 Pages

Scroll/Zoom	100%

制造商	WOLFSON [Wolfson Microelectronics plc]

网页	http://www.wolfsonmicro.com

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29 / 44 page

Production Data

WM8955BL

PD Rev 4.1 February 2007

MASTER CLOCK AND PHASE LOCKED LOOP

The WM8955BL has an on-chip phase-locked loop (PLL) circuit that can be used to:

•

generate a master clock for the WM8955BL audio function from another external clock,

e.g. in telecoms applications.

The PLL circuit is shown below.

DIGITAL

CORE

MCLK

f/2

PLL

MCLK

SEL

MCLK

DIV2

f/4

f/2

PLLOUT

DIV2

R = f

2 / f1

Figure 17 PLL Circuit

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R8 (08h)

Sample Rates

MCLKDIV2

MCLK Divide by 2

0: Divide disabled

1: Divide enabled

MCLKSEL

Select internal master clock

0: from MCLK pin

1: from PLL (make sure PLLEN=1)

PLLOUTDIV2

PLL Output Divide by 2

0: Divide disabled

1: Divide enabled

PLL_RB

0: PLL held in reset

1: PLL running (if PLLEN=1)

R43 (2Bh)

Clocking and

PLL

PLLEN

PLL Enable

0: PLL disabled; 1: PLL enabled.

Table 19 PLL and Clocking Control

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