WM8955BLGECOSLASHV datasheet(12/44 Pages) WOLFSON

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WM8955BL

Production Data

PD Rev 4.1 February 2007

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

MCLK

MCLKL

MCLKH

MCLKY

Figure 1 System Clock Timing Requirements

Test Conditions

CLKDIV2 = 0, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25

oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,

unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK System clock pulse width high

TMCLKL

MCLK System clock pulse width low

TMCLKH

MCLK System clock cycle time

TMCLKY

MCLK duty cycle

TMCLKDS

60:40

40:60

Test Conditions

CLKDIV2 = 1, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25

oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,

unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK System clock pulse width high

TMCLKL

MCLK System clock pulse width low

TMCLKH

MCLK System clock cycle time

TMCLKY

AUDIO INTERFACE TIMING – MASTER MODE

BCLK

(Output)

DACLRC

(Output)

DACDAT

DST

DHT

Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)

Test Conditions

DBVDD = 3.3V, DGND = 0V, TA = +25

oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Bit Clock Timing Information

BCLK rise time (10pF load)

tBCLKR

BCLK fall time (10pF load)

tBCLKF

BCLK duty cycle (normal mode, BCLK =

MCLK/n)

tBCLKDS

50:50

BCLK duty cycle (USB mode, BCLK = MCLK)

tBCLKDS

TMCLKDS

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WM8955BLGECO/V 数据表(PDF) 12 Page - Wolfson Microelectronics plc

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