22

3387L–DFLASH–6/06

AT45DB321C

Note:

1. Maximum specified frequency for SPI compatibility is 33 MHz.

2. The device uses an adaptive algorithm during program and erase operations. Use the RDY/BUSY bit of the status register or

the RDY/BUSY pin to determine whether the program or erase operation has completed. Fixed timing should not be used.

3. Value are based on device characterization, not 100% tested in production.

Table 10-4.

AC Characteristics – Serial Interface

Symbol

Parameter

Min

Typ

Max

Units

(1)

SCK Frequency

40

MHz

f

CAR

(1)

SCK Frequency for Continuous Array Read

40

MHz

t

WH

SCK High Time

10

ns

SCK Low Time

10

ns

t

CS

Minimum CS High Time

250

ns

CS Setup Time

100

ns

CS Hold Time

250

ns

t

CSB

CS High to RDY/BUSY Low

150

ns

Data In Setup Time

3

ns

Data In Hold Time

6

ns

t

HO

Output Hold Time

0

ns

Output Disable Time

10

ns

Output Valid

12

ns

t

XFR

Page to Buffer Transfer/Compare Time

350

µs

tEP

(2)(3)

Page Erase and Programming Time

16

50

ms

tP

(2)(3)

Page Programming Time

8

15

ms

t

PE

(2)(3)

Page Erase Time

8

35

ms

tBE

(2)(3)

Block Erase Time

20

100

ms

t

RST

RESET Pulse Width

10

µs

t

REC

RESET Recovery Time

1

µs

WP Low to Protection Enabled

1

µs

t

WPD

WP High to Protection Disabled

1

µs