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AT89LP213 数据表(PDF) 23 Page - ATMEL Corporation |
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AT89LP213 数据表(HTML) 23 Page - ATMEL Corporation |
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23 / 90 page ![]() 23 3538A–MICRO–7/06 AT89LP213/214 [Preliminary] . 13.1.1 Quasi-bidirectional Output Port pins in quasi-bidirectional output mode function similar to standard 8051 port pins. A Quasi- bidirectional port can be used both as an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin is driven low, it is driven strongly and able to sink a large current. There are three pull-up transistors in the quasi-bidirectional output that serve different purposes. One of these pull-ups, called the “very weak” pull-up, is turned on whenever the port latch for the pin contains a logic “1”. This very weak pull-up sources a very small current that will pull the pin high if it is left floating. A second pull-up, called the “weak” pull-up, is turned on when the port latch for the pin contains a logic “1” and the pin itself is also at a logic “1” level. This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a “1”. If this pin is pulled low by an external device, this weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the pin low under these conditions, the external device has to sink enough current to overpower the weak pull-up and pull the port pin below its input threshold voltage. The third pull-up is referred to as the “strong” pull-up. This pull-up is used to speed up low-to- high transitions on a quasi-bidirectional port pin when the port latch changes from a logic “0” to a logic “1”. When this occurs, the strong pull-up turns on for two CPU clocks quickly pulling the port pin high. The quasi-bidirectional port configuration is shown in Figure 13-1. The input cir- cuitry of P1.3, P3.2 and P3.3 is not disabled during Power-down (see Figure 13-3). Figure 13-1. Quasi-bidirectional Output Table 13-2. Configuration Modes for Port x, Bit y PxM0.y PxM1.y Port Mode 0 0 Quasi-bidirectional 0 1 Push-pull Output 1 0 Input Only (High Impedance) 1 1 Open-drain Output 1 Clock Delay (D Flip-Flop) Strong Very Weak Weak Port Pin VCC VCC VCC From Port Register Input Data PWD |
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