AT89LP213 datasheet(41/90 Pages) ATMEL

41 / 90 page

3538A–MICRO–7/06

AT89LP213/214 [Preliminary]

17.3

More About Mode 0

Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are trans-

mitted/received, with the LSB first. The baud rate is fixed at 1/2 the oscillator frequency. Figure

17-1 on page 42 shows a simplified functional diagram of the serial port in Mode 0 and associ-

ated timing.

Transmission is initiated by any instruction that uses SBUF as a destination register. The “write

to SBUF” signal also loads a “1” into the 9th position of the transmit shift register and tells the TX

Control Block to begin a transmission. The internal timing is such that one full machine cycle will

elapse between “write to SBUF” and activation of SEND.

SEND transfers the output of the shift register to the alternate output function line of P3.0, and

also transfers Shift Clock to the alternate output function line of P3.1. At the falling edge of Shift

Clock the contents of the transmit shift register are shifted one position to the right.

As data bits shift out to the right, “0”s come in from the left. When the MSB of the data byte is at

the output position of the shift register, the “1” that was initially loaded into the 9th position is just

to the left of the MSB, and all positions to the left of that contain “0”s. This condition flags the TX

Control block to do one last shift, then deactivate SEND and set TI.

Reception is initiated by the condition REN = 1 and R1 = 0. At the next clock cycle, the RX Con-

trol unit writes the bits 11111110 to the receive shift register and activates RECEIVE in the next

clock phase.

RECEIVE enables Shift Clock to the alternate output function line of P3.1. At the falling edge of

Shift Clock the contents of the receive shift register are shifted one position to the left. The value

that comes in from the right is the value that was sampled at the P3.0 pin at rising edge of Shift

Clock.

As data bits come in from the right, “1”s shift out to the left. When the “0” that was initially loaded

into the right-most position arrives at the left-most position in the shift register, it flags the RX

Control block to do one last shift and load SBUF. Then RECEIVE is cleared and RI is set.

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