T89C51RD2-RDTIL datasheet(94/104 Pages) ATMEL

94 / 104 page

T89C51RD2

4243G–8051–05/03

Clock Waveforms

Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.

This diagram indicates when signals are clocked internally. The time it takes the signals

to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is

dependent on variables such as temperature and pin loading. Propagation also varies

from output to output and component. Typically though (T

A=25°C fully loaded) RD and

WR propagation delays are approximately 50ns. The other signals are typically 85 ns.

Propagation delays are incorporated in the AC specifications.

DATA

PCL OUT

DATA

PCL OUT

DATA

PCL OUT

SAMPLED

STATE4

STATE5

STATE6

STATE1

STATE2

STATE3

STATE4

STATE5

FLOAT

THESE SIGNALS ARE NOT ACTIVATED DURING THE

EXECUTION OF A MOVX INSTRUCTION

INDICATES ADDRESS TRANSITIONS

EXTERNAL PROGRAM MEMORY FETCH

FLOAT

DATA

SAMPLED

DPL OR Rt OUT

INDICATES DPH OR P2 SFR TO PCH TRANSITION

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

PCL OUT (EVEN IF PROGRAM

MEMORY IS INTERNAL)

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

OLD DATA NEW DATA

P0 PINS SAMPLED

P1, P2, P3 PINS SAMPLED

P0 PINS SAMPLED

RXD SAMPLED

INTERNAL

CLOCK

XTAL2

ALE

PSEN

P2 (EXT)

READ CYCLE

WRITE CYCLE

PORT OPERATION

MOV PORT SRC

MOV DEST P0

MOV DEST PORT (P1. P2. P3)

(INCLUDES INTO. INT1. TO T1)

SERIAL PORT SHIFT CLOCK

TXD (MODE 0)

DATA OUT

DPL OR Rt OUT

INDICATES DPH OR P2 SFR TO PCH TRANSITION

RXD SAMPLED

T89C51RD2-RDTIL 数据表(PDF) 94 Page - ATMEL Corporation

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