T89C51RD2-RDTIL datasheet(43/104 Pages) ATMEL

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T89C51RD2

4243G–8051–05/03

Table 26. Minimum Reset Capacitor Value for a 50 k

Ω Pull-down Resistor(1)

Note:

These values assume V

DD starts from 0V to the nominal value. If the time between 2

on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully

discharged, leading to a bad reset sequence.

Warm Reset

To achieve a valid reset, the reset signal must be maintained for at least 2 machine

cycles (24 oscillator clock periods) while the oscillator is running. The number of clock

periods is mode independent (X2 or X1).

Watchdog Reset

As detailed in Section “Watchdog Timer”, the WDT generates a 96-clock period pulse

on the RST pin. In order to properly propagate this pulse to the rest of the application in

case of external capacitor or power-supply supervisor circuit, a 1 k

Ω resistor must be

added as shown Figure 18.

Figure 18. Reset Circuitry for WDT Reset-out Usage

Oscillator

Start-Up Time

VDD Rise Time

1 ms

10 ms

100 ms

5 ms

820 nF

1.2 µF

12 µF

20 ms

2.7 µF

3.9 µF

12 µF

RST

VSS

To CPU Core

and Peripherals

VDD

From WDT

Reset Source

VSS

VDD

RST

To Other

On-board

Circuitry

T89C51RD2-RDTIL 数据表(PDF) 43 Page - ATMEL Corporation

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