T89C51RD2-RDTIL datasheet(57/104 Pages) ATMEL

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T89C51RD2

4243G–8051–05/03

Table 35. Default Values

After programming the part by ISP, the BSB must be reset (00h) in order to allow the

application to boot at 0000h.

The content of the Software Security Byte (SSB) is described in Table 30 and Table 31

To assure code protection from a parallel access, the HSB must also be at the required

level.

The three lock bits provide different levels of protection for the on-chip code and data,

when programmed according to Table 31.

Table 36. Program Lock bits of the SSB

Note:

U: unprogrammed or "one" level.

Note:

P: programmed or "zero" level.

Note:

X:do not care

Note:

WARNING: Security level 2 and 3 should only be programmed after Flash and code

verification.

Mnemonic

Default Value

BSB

Boot Status Byte

FFh

SBV

Software Boot Vector

FCh

HSB

Copy of the Hardware security byte

18h or 1Bh

SSB

Software Security Byte

FFh

Copy of the Manufacturer Code

58h

ATMEL Wireless and

Microcontrollers

Copy of the Device ID #1: Family Code

D7h

C51 X2, Electrically Erasable

Copy of the Device ID #2: memories size

and type

FCh

T89C51RD2 memories

size

Copy of the Device ID # 3: name and

revision

FFh

T89C51RD2, revision 0

Program Lock Bits

Protection Description

Security

level

LB0

LB1

No program lock features enabled.

following commands are disabled:

- program byte

- program status byte and boot vector

- erase status byte and boot vector

Same as 2 and following commands also disabled:

- read byte

- read status byte and boot vector

- blank check

- program SSB level2

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