T89C51RD2-RDTIM datasheet(17/104 Pages) ATMEL

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T89C51RD2

4243G–8051–05/03

Table 7. Auxiliary Register (08EH)

AUXR

Address 08EH

XRS1

XRS0

EXTRA

Reset value

Symbol

Function

Not implemented, reserved for future use.

(1)

User software should not write 1s to reserved bits. These bits may be used in future 8051

family products to invoke new features. In that case, the reset or inactive value of the

new bit will be 0, and its active value will be 1. The value read from a reserved bit is

indeterminate.

Disable/Enable ALE

Operating Mode

ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2

mode is used)

ALE is active only during a MOVX or MOVC instruction

EXTRAM

Internal/External RAM (00H-FFH) access using MOVX @ Ri/ @ DPTR

EXTRAM

Operating Mode

Internal XRAM access using MOVX @ Ri/ @ DPTR

External data memory access

XRS0

XRS1

XRAM size: Accessible size of the XRAM

XRS1:0

XRAM size

0 0

256 bytes

0 1

512 bytes

1 0

768 bytes (default)

1 1

1024 bytes

Stretch MOVX control: the RD/ and the WR/ pulse length is increased according to the

value of M0

Pulse length in clock period

130

T89C51RD2-RDTIM 数据表(PDF) 17 Page - ATMEL Corporation

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