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T89C51RD2-RDTIM 数据表(PDF) 36 Page - ATMEL Corporation

部件名 T89C51RD2-RDTIM
功能描述  0 to 40 MHz Flash Programmable 8-bit Microcontroller
PDF  104 Pages
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制造商  ATMEL [ATMEL Corporation]
网页  http://www.atmel.com
标志 ATMEL - ATMEL Corporation

T89C51RD2-RDTIM 数据表(HTML) 36 Page - ATMEL Corporation

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36
T89C51RD2
4243G–8051–05/03
Table 19. SADDR - Slave Address Register (A9h)
Reset Value = 0000 0000b
Not bit addressable
Table 20. SCON Register
SCON - Serial Control Register (98h)
Reset Value = 0000 0000b
Bit addressable
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Number
Bit
Mnemonic
Description
7FE
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
SM0
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
6SM1
Serial port Mode bit 1
SM0 SM1
Mode Description
Baud Rate
0
0
0
Shift Register F
XTAL/12 (/6 in X2 mode)
0
1
1
8-bit UART
Variable
1
0
2
9-bit UART
FXTAL/64 or FXTAL/32 (/32 or 16 in X2 mode)
1
1
3
9-bit UART
Variable
5SM2
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1. This bit should be cleared in mode 0.
4REN
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
3TB8
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
2RB8
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1TI
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of
the stop bit in the other modes.
0RI
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 14. and
Figure 15. in the other modes.



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