CC1110-RTY1 datasheet(62/203 Pages) TI

62 / 203 page

CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 62 of 202

•

IEN2.P2IE : P2 interrupt enable

In addition to these common interrupt enables,

the bits within each port have interrupt enables

located in I/O port SFR registers. Each bit

within P1 has an individual interrupt enable. In

P0 the low-order nibble and the high-order

nibble have their individual interrupt enables.

For the P2_0 – P2_4 inputs there is a common

interrupt enable.

When an interrupt condition occurs on one of

the

general

purpose

I/O

pins,

the

corresponding interrupt status flag in the P0-

P2 interrupt flag registers, P0IFG , P1IFG or

P2IFG will be set to 1. The interrupt status flag

is set regardless of whether the pin has its

interrupt enable set. When an interrupt is

serviced the interrupt status flag is cleared by

writing a 0 to that flag.

Note that when clearing the PxIFG interrupt

status flags, only one active flag should be

cleared at a time. Failure to do this may result

in generation of false interrupt requests.

The SFR registers used for I/O interrupts are

described in section 12.7 on page 45. The

registers are summarized below:

•

P1IEN : P1 interrupt enables

•

PICTL : P0/P2 interrupt enables and P0-2

edge configuration

•

P0IFG : P0 interrupt flags

•

P1IFG : P1 interrupt flags

•

P2IFG : P2 interrupt flags

13.1.3 General Purpose I/O DMA

When used as general purpose I/O pins, the

P0 and P1 ports are each associated with one

DMA trigger. These DMA triggers are IOC_0

for P0 and IOC_1 for P1 as shown in Table 37

on page 84.

The IOC_0 or IOC_1 DMA trigger is activated

when an input transition occurs on one of the

P0 or P1 pins respectively. Note that only input

transitions on pins configured as general

purpose I/O inputs, will produce the DMA

trigger.

13.1.4 Peripheral I/O

This

section

describes how

the digital

input/output pins are configured as peripheral

I/Os. For each peripheral unit that can

interface with an external system through the

digital input/output pins, a description of how

peripheral I/Os are configured is given in the

following sub-sections.

In general, setting the appropriate PxSEL bits

to 1 is required to select peripheral I/O function

on a digital I/O pin.

Note that peripheral units have two alternative

locations for their I/O pins, refer to Table 36.

The location to be used is selected by writing

to PERCFG.

It is possible to set PERCFG so that several

peripherals are assigned to the same port

pins. In such cases a set of peripheral priority

control bits select the order of precedence

between up to two peripherals at a time, when

these are assigned to the same port pins.

CC1110-RTY1 数据表(PDF) 62 Page - Texas Instruments

CC1110-RTY1 数据表(HTML) 62 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载