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CC1110-RTY1 数据表(PDF) 81 Page - Texas Instruments |
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CC1110-RTY1 数据表(HTML) 81 Page - Texas Instruments |
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81 / 203 page  CC1110 CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A Page 81 of 202 3. Transfer number of bytes/words commanded by first byte/word + 2 (transfers length byte/word, and then as many bytes/words as dictated by length byte/word + 1) 4. Transfer number of bytes/words commanded by first byte/word + 3 (transfers length byte/word, and then as many bytes/words as dictated by length byte/word + 2) LENGTH=n byte/word 1 byte/word 2 byte/word 3 byte/word n-1 byte/word n LENGTH=n byte/word 1 byte/word 2 byte/word 3 byte/word n-1 byte/word n LENGTH=n byte/word 1 byte/word 2 byte/word 3 byte/word n-1 byte/word n LENGTH=n byte/word 1 byte/word 2 byte/word 3 byte/word n-1 byte/word n byte/word n+1 byte/word n+1 byte/word n+2 VLEN=001 VLEN=010 VLEN=011 VLEN=100 Figure 11: Variable Length (VLEN) Transfer Options 13.2.2.5 Trigger Event Each DMA channel can be set up to sense on a single trigger. This field determines which trigger the DMA channel shall sense. 13.2.2.6 Source and Destination Increment When the DMA channel is armed or rearmed the source and destination addresses are transferred to internal address pointers. The possibilities for address increment are : • Increment by zero. The address pointer shall remain fixed after each transfer. • Increment by one. The address pointer shall increment one count after each transfer. • Increment by two. The address pointer shall increment two counts after each transfer. • Decrement by one. The address pointer shall decrement one count after each transfer. 13.2.2.7 DMA Transfer Mode The transfer mode determines how the DMA channel behaves when it starts transferring data. There are four transfer modes described below: Single . On a trigger a single DMA transfer occurs and the DMA channel awaits the next trigger. After the number of transfers specified by the transfer count are completed, the CPU is notified and the DMA channel is disarmed. Block . On a trigger the number of DMA transfers specified by the transfer count is performed as quickly as possible, after which the CPU is notified and the DMA channel is disarmed. Repeated single. On a trigger a single DMA transfer occurs and the DMA channel awaits the next trigger. After the number of transfers specified by the transfer count are completed, the CPU is notified and the DMA channel is rearmed. Repeated block. On a trigger the number of DMA transfers specified by the transfer count is performed as quickly as possible, after |
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