ADA4351-2ACPZ-R7 datasheet(26/36 Pages) AD

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Data Sheet

ADA4351-2

THEORY OF OPERATION

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Rev. 0 | 26 of 36

Figure 84. Output Headroom (HR) to AVDD vs. RF

MAIN AMPLIFIER (CMOS)

Rail-to-Rail Output Stage

For a TIA in a single-supply configuration with a unidirectional input

signal (see Figure 85), the minimum detectable signal is directly

impacted by the input and output swing limits of the amplifier. For

this circuit to maintain best linearity, the reference voltage, VREF,

(noninverting input) must be biased at 0.1 V or higher to satisfy the

0.1 V output headroom above the negative supply.

Figure 85. ADA4351-2 Single-Supply Operation

For the output to be able to swing to GND, the analog part of

the amplifier must be operated on a negative supply that is less

than GND, usually −0.2 V to −0.5 V. Because the ADA4351-2 has

separate digital supplies, DVDD and DVSS, the logic threshold

levels are independent of the analog supplies, so the analog portion

can run on split supplies or a negative supply slightly less than

GND. The ADA4351-2 was designed with a rail-to-rail output stage

and can operate to within 100 mV from the power supplies with AOL

> 110 dB, which provides flexibility for the system and eases design

constraints.

Bottom Rail Input Stage

The VREF shown in Figure 85 is constrained by the input common-

mode range of the main amplifier. In a single-supply configuration,

VREF sets the minimum output voltage value; therefore, the dynamic

range is constrained between VREF and the maximum ADC input

voltage. The ADA4351-2 was designed with a PMOS input differ-

ential pair to allow the analog inputs to swing to AVSS, where

AVSS can be set to as much as 0.5 V less than DVSS. It is less

common in TIA designs for the input common-mode voltage across

the inputs to approach the positive supply. The ADA4351-2 input

stage requires 1.5 V headroom to the positive supply. Alternative

approaches to supporting a rail-to-rail input are to either add a

second input pair or an on-board charge pump to bias the input

stage more than the supply. However, the first approach creates

a large offset voltage in the crossover region, while the second

approach adds quiescent power and switching noise to the design.

Low Noise Operation

In a transimpedance amplifier, having low op-amp input voltage

noise is particularly crucial. At low frequency, the noise gain is near

1 V/V. However, at higher frequencies, the noise gain increases

from zero due to CS (see the TIA Design Theory section). Addition-

ally, more noise is integrated (per decade) at higher frequencies,

which contributes to the total output integrated noise. While there is

usually a design trade-off between noise and power consumption,

the ADA4351-2 contributes 7.3 nV/√Hz of wideband noise while

requiring only 3.3 mA per channel.

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