ADA4351-2ACPZ-R7 datasheet(23/36 Pages) AD

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Data Sheet

ADA4351-2

THEORY OF OPERATION

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Rev. 0 | 23 of 36

OVERVIEW

The ADA4351-2 is a small, dual-channel precision PGTIA designed

to maximize system dynamic range by minimizing errors associated

with a PGTIA signal chain while reducing overall PCB footprint

requirements. The main amplifier has low offset voltage over tem-

perature, low noise, and low input bias current and is designed

to drive an analog-to-digital converter (ADC) directly. The propriet-

ary low off-leakage switches used to select one of two feedback

paths outperform typical CMOS switches of similar size and on

resistance. The switches are arranged in a Kelvin configuration that

removes the nonlinear behavior of the CMOS switch on resistance

from the transfer function. With two possible external feedback

paths and a direct ADC drive, this dual-channel PGTIA significantly

reduces the PCB footprint requirements compared to a discrete

solution. Additionally, the PGTIA is internally compensated with a

3 pF internal feedback capacitor for gains >50 kΩ, assuming a

source capacitance (CS) of approximately 10 pF, which eliminates

the need for an external compensation capacitor, in most cases,

further reducing the required PCB footprint.

The analog circuitry operates on either a single supply (+2.7 V to

+5.5 V) or a dual supply (±1.35 V to ±2.75 V) with a rail-to-rail

output stage and a negative-rail input stage to provide user flexibili-

ty for unidirectional or bidirectional input current signals as well as

directly driving an ADC with a voltage reference up to 5.5 V. The

digital input (switch control) operates on supplies between 1.62 V

and 5.5 V to interface directly with standard logic levels (1.8, 3.3,

or 5) based on the voltage applied to the digital supply (DVSS and

DVDD). The voltage levels required for a logic low or high value

(VIH/VIL) are based on the digital input voltage (SW SEL) relative to

the corresponding digital rail (DVSS and DVDD).

The switches for Channel A and Channel B of the ADA4351-2

are controlled by the digital inputs, SW SEL A and SW SEL

B, respectively. The logic low and high threshold is based on

the digital power supply voltages (DVSS and DVDD, see Table

1 and Table 2 for more information). The digital supplies in the

ADA4351-2 are included to provide the user flexibility to control

the switch logic separately from the analog supply range as these

two ranges are not typically the same. The ADA4351-2 includes

level shifting circuitry to translate the switch control signals from

digital domain to the analog domain which simplifies the design

compared to a discrete solution. The two internal switch selections

are make-before-break to maintain a closed feedback loop during

switching to eliminate output overdrive glitches that would otherwise

occur.

To simplify terminology, because the two amplifiers inside the

ADA4351-2 are interchangeable, RF1, RF0, SW0, SW1, SW SEL,

+IN, and −IN refer to Channel A or Channel B. VOUT refers to OUTA

or OUTB, and within each channel, RF refers to RF1 or RF0.

PGTIA ERRORS

PGTIA Measurements

The ADA4351-2 is designed for high accuracy transimpedance

measurements for TIA gains from 200 Ω to beyond 10 MΩ.

Because different and competing error sources dominate at the

extremes of TIA gains, the ADA4351-2 is designed to be optimal

for any gain configuration (see the Switch Off Leakage Current

section for additional information). For lower TIA gain values, the

dominant output DC error source is the input offset voltage, while

for higher TIA gain values, the dominant output DC error source

is the input bias current and the switch off leakage current. The

following sections outline the leading errors in a PGTIA circuit.

The PGTIA circuit (see Figure 78) models a capacitive sensor with

a current source (that is, a photodiode) into the inverting junction

of a closed-loop op amp. This virtual ground passes the +IN bias

voltage over to the inverting summing junction as part of the diode

bias voltage and sinks all of the photodiode current from the output

pin through the feedback resistor. The photodiode is modeled as

a shunt capacitance (CD) and shunt resistance (RSH) in parallel

with the current source. Any signal current from the sensor flows

through the selected feedback path of the PGTIA, where the ideal

transfer function of the PGTIA is VOUT = diode current (ID) × RF0

(because the RF0 gain path is selected). When photodiode DC dark

current (IDARK) is significant, such as when a large reverse bias

voltage (−VB) is applied), it may also be included in the source

model.

Figure 78. PGTIA Circuit

Offset Voltage

The offset voltage of the amplifier in a PGTIA limits the minimum

detectable signal in the system at low gains. The error at the output

of the PGTIA due to the amplifier TIA offset is gained up by the

(DC) noise gain of the amplifier (1 + RF/RSH for a typical inverting

amplifier), where RSH is any shunt resistance in the photodiode

model. For RSH >> RF, this reduces to 1. Because the offset is a

voltage error, it impacts the usable and accurate codes of the ADC

for all TIA gains in a similar way. The ADA4351-2 uses proprietary

in-package offset and offset-drift trim that allow it to achieve a

maximum of 100 µV offset voltage at 25°C and 0.85 µV/°C drift

from −40°C to +125°C at a 5 V supply.

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