ADA4351-2ACPZ-R7 datasheet(35/36 Pages) AD

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Data Sheet

ADA4351-2

APPLICATIONS INFORMATION

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Rev. 0 | 35 of 36

PCB LAYOUT

In high source impedance applications, the low input bias current of

the ADA4351-2 requires a clean PCB layout to minimize addition-

al leakage current into a high impedance signal node. A layout

recommendation for any PCB designed with this device is to strip

the conductor around the signal carrying trace as shown in Figure

98. This stripping makes it more difficult for leakage currents from

the PCB to couple into the signal path, causes output errors, and

minimizes parasitic capacitance at the inputs.

It is important to keep the high impedance signal path as short as

possible on the PCB. A node with high impedance is susceptible to

picking up any stray signals in the system; therefore, keeping the

path as short as possible reduces this effect. Additionally, the longer

the signal trace into the PCB (on the inverting input) the more stray

capacitance at the input of the device under test (DUT). A trace

capacitance as low as 5 pF can greatly impact board performance,

especially if the photodiode or current source used is around the

same order of magnitude of capacitance .

Other signals must be routed well away from the signal path, and

there must be no internal power planes under the high impedance

node. The best defense from coupling signals is shielding; however,

this increases capacitance in the area, which impacts the noise

gain of the PCB. Another method to decouple signals is distance,

which includes vertically (though layers of the PCB) as well as on

the surface of the PCB. The package of the ADA4351-2 aids with

this routing process because there is no exposed pad (EPAD) on

the back side of the package, eliminating the need for vias and

allowing routing on all layers of the PCB beneath the device. In

cases where the space is limited, the designer can cut slots in the

PCB around the high impedance input nodes to provide additional

isolation and to reduce the chance of contamination on the surface

of the PCB.

Figure 98. Example PCB Layout for Low Surface Leakage

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