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ADA4351-2ACPZ-R7 数据表(PDF) 8 Page - Analog Devices |
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ADA4351-2ACPZ-R7 数据表(HTML) 8 Page - Analog Devices |
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8 / 36 page ![]() Data Sheet ADA4351-2 ABSOLUTE MAXIMUM RATINGS analog.com Rev. 0 | 8 of 36 Table 3. Absolute Maximum Ratings Parameter Rating Voltage Between Any Two Pins 6 V DVDD and AVDD to DVSS −0.3 V to +6 V DVDD, AVDD, and DVSS to AVSS −0.3 V to +6 V +IN and −IN Voltage AVSS − 1 V to AVDD + 1 V +IN and −IN Current 10 mA SW0 and SW1 Voltage AVSS − 0.3 V to AVDD + 0.3 V SW SEL Voltage DVSS − 0.3 V to DVDD + 0.3 V SW SEL Current 10 mA Op Amp Output Continuous Current ±20 mA1, electromigration limited Switch Continuous Current ±20 mA1, electromigration limited Temperature Storage Range −65°C to +150°C Operating Range −40°C to +125°C Junction, TJ 150°C Case, TC 260°C 1 Specified at 100°C. See the derating curve for temperatures beyond 100°C (see Figure 4). Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operat- ing conditions for extended periods may affect product reliability. THERMAL RESISTANCE Thermal performance is directly linked to PCB design and operating environment. Careful attention to PCB thermal design is required. θJA is the natural convection junction-to-ambient thermal resistance measured in a one cubic foot sealed enclosure. Table 4. Thermal Resistance Package Type θJA Unit CP-16-32 91 °C/W MAXIMUM POWER DISSIPATION The maximum safe power dissipation for the ADA4351-2 is limited by the associated rise in TJ on the die. At approximately 150°C, which is the glass transition temperature, the properties of the plas- tic change. Even temporarily exceeding this temperature limit may change the stresses the package exerts on the die, permanently shifting the parametric performance of the ADA4351-2. Exceeding a TJ of 175°C for an extended period can result in changes in the sili- con devices, potentially causing degradation or loss of functionality. The power dissipated in the package is the sum of the quiescent power dissipation and the power dissipated in the die due to the output load drive of the amplifier. OUTPUT CURRENT DERATING CURVE Figure 4. Maximum Output Current Derating Curve vs. Temperature EXPLANATION OF TEST LEVELS Table 5. Explanation of Test Levels Test Level Description D Definition S Design verification simulation P 100% production tested PF Functionally checked during production test CT Characterized on tester CB Characterized on bench |
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