AM29PL160CB-65REF datasheet(19/44 Pages) AMD

19 / 44 page

May 9, 2006 22143C7

Am29PL160C

D A TA

SH EE T

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may

halt the operation and set DQ5 to “1,” or cause the

Data# Polling algorithm to indicate the operation was

successful. However, a succeeding read will show that

the data is still “0”. Only erase operations can convert

a “0” to a “1”.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram bytes or words to the device faster than using the

standard program command sequence. The unlock by-

pass command sequence is initiated by first writing

two unlock cycles. This is followed by a third write cycle

containing the unlock bypass command, 20h. The de-

vice then enters the unlock bypass mode. A two-cycle

unlock bypass program command sequence is all that

is required to program in this mode. The first cycle in

this sequence contains the unlock bypass program

command, A0h; the second cycle contains the pro-

g r a m ad dre ss an d d a ta . Additio n a l da ta is

programmed in the same manner. This mode dis-

penses with the initial two unlock cycles required in the

standard program command sequence, resulting in

faster total programming time. Table 10 shows the re-

quirements for the command sequence.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the data

90h; the second cycle the data 00h. Addresses are

don’t care for both cycles. The device then returns to

reading array data.

Figure 1 illustrates the algorithm for the program oper-

ation. See the Program/Erase Operations table in “AC

Characteristics” for parameters, and to Figure 15 for

timing diagrams.

Note: See Table 10 for program command sequence.

Figure 1.

Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 10

shows the address and data requirements for the chip

erase command sequence.

Any commands written to the chip during the Embed-

ded Erase algorithm are ignored.

The system can determine the status of the erase op-

eration by using DQ7, DQ6, or DQ2. See “Write

Operation Status” for information on these status bits.

When the Embedded Erase algorithm is complete, the

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

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