AM29PDS322D datasheet(12/51 Pages) AMD

12 / 51 page

Am29PDS322D

23569A5 December 4, 2006

D A TA

SH EE T

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

CC3 in the DC Characteristics table represents the

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for t

ACC +

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when ad-

dresses are changed. While in sleep mode, output

data is latched and always available to the system.

Automatic sleep mode current is drawn when CE# =

SS ± 0.3 V and all inputs are held at VCC ± 0.3 V. If

CE# and RESET# voltages are not held within these

tolerances, the automatic sleep mode current will be

greater.

CC5 in the DC Characteristics table represents the

automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t

RP, the

device immediately ter minates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V

SS ± 0.3 V, the device

draws CMOS standby current (I

CC3). If RESET# is held

at V

IL but not within VSS ± 0.3 V, the standby current

will be greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t

READY (during Embedded Algorithms). The sys-

tem can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t

READY (not during Embedded Algo-

rithms). The system can read data t

RH after the RE-

SET# pin returns to V

IH.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 17 for the timing diagram.

Output Disable Mode

When the OE# input is at V

IH, output from the device is

disabled. The output pins are placed in the high

impedance state.

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