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D640D90VF 数据表(PDF) 38 Page - Advanced Micro Devices |
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D640D90VF 数据表(HTML) 38 Page - Advanced Micro Devices |
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38 / 54 page ![]() 36 Am29DL640D December 13, 2005 AC CHARACTERISTICS Read-Only Operations Notes: 1. Not 100% tested. 2. See Figure 12 and Table 14 for test specifications 3. Measurements performed by placing a 50 Ω termination on the data pin with a bias of V CC/2. The time from OE# high to the data bus driven to V CC/2 is taken as tDF . Parameter Description (Notes) Test Setup Speed Options JEDEC Std. 90 120 Unit t AVAV t RC Read Cycle Time (1) Min 90 120 ns t AVQV t ACC Address to Output Delay CE#, OE# = V IL Max 90 120 ns t ELQV t CE Chip Enable to Output Delay OE# = V IL Max 90 120 ns t GLQV t OE Output Enable to Output Delay Max 35 50 ns t EHQZ t DF Chip Enable to Output High Z (1, 3) Max 30 ns t GHQZ t DF Output Enable to Output High Z ( 1, 3) Max 30 ns t AXQX t OH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Min 0 ns t OEH Output Enable Hold Time (1) Read Min 0 ns Toggle and Data# Polling Min 10 ns tOH tCE Outputs WE# Addresses CE# OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tRH tOE tRH 0 V RY/BY# RESET# tDF Figure 14. Read Operation Timings |
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