D640D90VF datasheet(12/54 Pages) AMD

12 / 54 page

Am29DL640D

December 13, 2005

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for t

ACC +

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dr ess acc e ss t i mi ngs p r ov i de new da ta wh en

addresses are changed. While in sleep mode, output

data is latched and always available to the system.

ICC5 in the DC Characteristics table represents the

automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the

RESET# pin is driven low for at least a period of tRP,

the device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was

interrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VSS±0.3 V, the device

draws CMOS standby current (ICC4). If RESET# is

held at V

IL but not within VSS±0.3 V, the standby cur-

rent is greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t

READY (during Embedded Algorithms). The sys-

tem can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t

READY (not during Embedded Algo-

rithms). The system can read data t

RH after the

RESET# pin returns to V

IH.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 15 for the timing diagram.

Output Disable Mode

When the OE# input is at V

IH, output from the device is

disabled. The output pins are placed in the high

impedance state.

Table 2.

Am29DL640D Sector Architecture

Bank

Sector

Sector Address

A21–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

Bank 1

SA0

0000000000

8/4

000000h–001FFFh

00000h–00FFFh

SA1

0000000001

8/4

002000h–003FFFh

01000h–01FFFh

SA2

0000000010

8/4

004000h–005FFFh

02000h–02FFFh

SA3

0000000011

8/4

006000h–007FFFh

03000h–03FFFh

SA4

0000000100

8/4

008000h–009FFFh

04000h–04FFFh

SA5

0000000101

8/4

00A000h–00BFFFh

05000h–05FFFh

SA6

0000000110

8/4

00C000h–00DFFFh

06000h–06FFFh

SA7

0000000111

8/4

00E000h–00FFFFFh

07000h–07FFFh

SA8

0000001xxx

64/32

010000h–01FFFFh

08000h–0FFFFh

SA9

0000010xxx

64/32

020000h–02FFFFh

10000h–17FFFh

SA10

0000011xxx

64/32

030000h–03FFFFh

18000h–1FFFFh

SA11

0000100xxx

64/32

040000h–04FFFFh

20000h–27FFFh

SA12

0000101xxx

64/32

050000h–05FFFFh

28000h–2FFFFh

SA13

0000110xxx

64/32

060000h–06FFFFh

30000h–37FFFh

SA14

0000111xxx

64/32

070000h–07FFFFh

38000h–3FFFFh

SA15

0001000xxx

64/32

080000h–08FFFFh

40000h–47FFFh

SA16

0001001xxx

64/32

090000h–09FFFFh

48000h–4FFFFh

SA17

0001010xxx

64/32

0A0000h–0AFFFFh

50000h–57FFFh

SA18

0001011xxx

64/32

0B0000h–0BFFFFh

58000h–5FFFFh

SA19

0001100xxx

64/32

0C0000h–0CFFFFh

60000h–67FFFh

SA20

0001101xxx

64/32

0D0000h–0DFFFFh

68000h–6FFFFh

SA21

0001110xxx

64/32

0E0000h–0EFFFFh

70000h–77FFFh

SA22

0001111xxx

64/32

0F0000h–0FFFFFh

78000h–7FFFFh

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