PCF5083HSLASH001SLASHF2 datasheet(41/136 Pages) PHILIPS

41 / 136 page

1996 Oct 29

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

8.5.8

EXTERNAL IOM®-2 INTERFACE

This block provides an IOM®-2 interface for external

devices and accessories e.g. digital handsfree equipment

data and fax interfaces etc. It is used as an interface to the

system simulator during type approval.

The external IOM®-2 interface (DCL, FSC, DU and DD) is

only enabled if the flag IOMCON_REG[IOMEXT_EN] is

set. Otherwise, unless in external clock mode, the outputs

DCL, FSC and DD are in their high-impedance state and

the input DU is don’t care (default after reset). In external

clock mode the flag IOMCON_REG[IOMEXT_EN] flag

only controls the data lines DU and DD. DCL and FSC are

inputs in this mode independently from the state of the flag.

If the flag IOMCON_REG[IOMEXT_INV] is set, all I/Os of

the external IOM®-2 interface are inverted to allow the use

of an external inverting driver circuit.

If the external IOM®-2 interface is disabled with

IOMCON_REG[IOMEXT_EN] = 0, the DU input is

externally pulled-up and will be monitored for a LOW level.

An external device has to pull-down this line to register

itself. If a LOW on DU was detected, the SI_INT interrupt

is activated with flag SIINT_REG[EXT_IOM] set. The flag

and therefore the interrupt condition is automatically

cleared after IOMCON_REG[IOMEXT_EN] was set.

8.6

MMI Interface

The PCF5083 provides a RS232 and a Power-down

interface to fully support the MMI controller TDA8005.

8.6.1

RS232 INTERFACE

This block provides a full RS232 interface with a fixed

8E1 protocol configuration.

The shift clock is derived from the 1 MHz clock for normal

operation. For test purposes a clock applied at input ADI is

used if SYSCON_REG[RS232_CLK] is set. The clock is

divided by 12

× 3 × 16 to derive the shift clock. This results

in a baud rate of 22569.44 Baud at 13 MHz. The receiver

works with an oversampling of 16.

8.6.1.1

Transmit

After writing to the register TXD_REG, the register content

is serially clocked out. The SIINT_REG[TXD_OBE] flag is

set and the SI_INT interrupt is generated (refer to

Section 10.2). The flag and therefore the interrupt

condition is cleared after writing the next data byte to

8.6.1.2

Receive

The incoming serial data stream is clocked into register

RXD_REG. SIINT_REG[RXD_IBF] is set after a data byte

was received and the SI_INT interrupt is generated. The

state of the RXD_IBF flag is available on the MMIEN

output and is used to implement a hardware handshake to

the TDA8005. The SIINT_REG[PAR_ERR] flag signals a

parity error and will be updated when the RXD_IBF flag

goes active. The RXD_IBF flag and therefore the interrupt

condition is cleared automatically after reading the register

RXD_REG.

Both interrupt conditions can be disabled with the

corresponding mask flags in SIMASK_REG. The flag

handling remains the same as described.

The output MMIEN is set to a logic 1 as long as

HWCTRL_REG[MMICLK] = 0.

Note that PAR_ERR is not used as an interrupt condition.

8.6.2

MMI POWER-DOWN INTERFACE

The MMI power-down interface controls the power

consumption of the MMI controller (MMIC) TDA8005 by

halting its main 13 MHz clock. The following signals are

used:

• MMICLK: 13 MHz clock output, main clock for the MMIC

• MMIREQ: MMI clock request input.

The MMI wake-up and power-down procedures are:

1. Force MMIC into power-down mode:

Set HWCTRL_REG[MMICLK] = 0 to stop the 13 MHz

MMI clock. The MMICLK output is held LOW and the

output MMIEN of the RS232 interface is set HIGH.

2. Wake-up MMIC via System Controller:

Set HWCTRL_REG[MMICLK] = 1 to activate

MMICLK.

3. Wake-up MMIC after keyboard or SIM card reader

activity:

In this case the MMIC generates a LOW-to-HIGH

transition on pin MMIREQ. The flags MMIREQ and

MMICLK in register HWCTRL_REG will be set and the

MMICLK output is activated. If the timing generator

unit (SGU) is in Sleep mode, a wake-up request is

issued to force the SGU into the wake-up state. In the

wake-up state HWCTRL_INT and MMICLK are

activated. The MMIREQ flag has to be explicitly

cleared by the System Controller.

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