PCF5083HSLASH001SLASHF2 datasheet(42/136 Pages) PHILIPS

42 / 136 page

1996 Oct 29

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

It should be noted that:

• A LOW-to-HIGH transition of MMIREQ is detected

independent of HWCTRL_REG[MMICLK] respectively.

• As long as HWCTRL_REG[MMICLK] = 1, the REFON

output stays active even if the SGU enters Sleep mode.

During power-up reset indicated with RST active LOW,

HWCTRL_REG[MMICLK] is set and MMICLK is activated.

8.7

General purpose parallel I/O port

The PCF5083 includes a 6-bit general purpose parallel I/O

port. Every I/O line, except PIO0, has a corresponding

data bit in PORTDATA_REG and a data direction bit in

PORTDDIR_REG. The bits in PORTDATA_REG directly

represent the state of the I/O pins if the port is configured

as an input. Otherwise if the port is configured as output,

the data written to PORTDATA_REG directly represents

the state of the port line. A logic 1 in PORTDDIR_REG

configures the port line as an output, a logic 0 as an input.

PIO0 is configured as output only. It is used internally to

drive the reset input of the DSP core.

8.8

Real Time Clock

A real time/alarm time clock unit is included in the timer

core. The clock unit is driven from the 32.768 kHz crystal

oscillator. A leap year function is included. The clock

function utilizes the registers/counters specified in

Table 26.

Table 26 Clock function registers/counters

REGISTERS/

COUNTERS

CLOCK FUNCTION

SEC_REG

seconds, 00 to 59, two 4-bit digits BCD

encoded

MIN_REG

minutes, 00 to 59, two 4-bit digits BCD

encoded

HOUR_REG

hours, 00 to 23, two 4-bit digits BCD

encoded

DAY_REG

day, 0 to 6, 0 = Monday to 6 = Sunday

DATE_REG

date, 0 to 31, two 4-bit digits BCD

encoded

MONTH_REG

month, 01 to 12, two 4-bit digits BCD

encoded

YEAR_REG

year, 00 to 99, two 4-bit digits BCD

encoded

If the flag HWCTRL_REG[SECINT] is reset, the hardware

control interrupt (HWCTRL_INT, refer to Section 10.2) is

asserted with the HWCTRL_REG[CLOCK] flag set every

time MIN_REG is incremented. Otherwise if the flag is set,

the interrupt is asserted every time SEC_REG is

incremented.

8.8.1

SETTING THE REAL TIME CLOCK

To set the real time clock, the SETCLOCK bit in

HWCTRL_REG must be set to a logic 1. The flag is then

polled until it is read as a logic 1 again. This action may last

up to 0.5 s. After SETCLOCK = 1 is detected, the clock

registers can be written. After the write operation

SETCLOCK has to be reset again. If the register setting

takes place immediately after the hardware control

interrupt was asserted, the clock registers may be written

without polling of the SETCLOCK flag (SETCLOCK still

has to be set prior and reset after the register write

operation).

The following should be noted:

• If the Sleep mode is invoked, a wake-up request is

generated every time the hardware control interrupt is

asserted. To increase performance it is not

recommended to use the interrupt facility at a rate of one

second during Sleep mode.

An alarm function is implemented using the registers

SEC_A_REG, MIN_A_REG, HOUR_A_REG,

DAY_A_REG, DATE_A_REG, MONTH_A_REG and

YEAR_A_REG. If the contents of these registers equals

the corresponding counters, the hardware control interrupt

is asserted with the flag HWCTRL_REG[ALARM] set. If all

bits are set to one in one of the registers (07H in case of

the DAY_A_REG) it is don’t care for the comparison. If the

alarm function is activated while the MS is switched off, the

MS is powered up as described in Section 8.2.1.

If RSTC is activated the clock counters are reset to 00H,

except date and month which are set to 01H.

MONTH_A_REG is set to 00H to avoid an alarm condition.

The other alarm registers are undefined.

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