PCF5083HSLASH001SLASHF2 datasheet(45/136 Pages) PHILIPS

45 / 136 page

1996 Oct 29

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

9.1.2

GMSK MODULATOR INTERFACE

The PCF5083 serial output port SOX is used to transmit

the coded, interleaved and formatted bits to the GMSK

modulator in the PCF5072 baseband interface IC.

The SOX port consists of:

• Serial Output Data signal (SOXD)

• Serial Output Clock signal (SOXCLK), running at

270.83 kHz

• Serial Output Enable signal (SOXEN), active LOW.

The GSM bit clock is directly used as the external shift

clock, therefore no external buffering of transmission data

is necessary.

The PCF5083 general purpose I/O pin IO4 is used to

enable or disable the transmitter during DTX. If IO4 = 0,

the transmitter is enabled. If IO4 = 1, the transmitter is

disabled. It is sampled by the TDMA timer at the beginning

of the transmit burst period.

9.1.2.1

Burst format

Tables 29 and 30 show the format of the normal and

access burst produced by the DSP. The period of the

8 leading bits allows the power amplifier to ramp-down and

ramp-up.

Table 29 Normal burst format

BITS

NUMBER

OF BITS

DESCRIPTION

0 to 7

dummy bits (set to logic 1)

8 to 155

148

BN0 to BN147 in accordance

with

“GSM Rec. 05.02”

Table 30 Access burst format

9.1.3

AUDIO AND DATA INTERFACE

The PCF5083 serial port Y is connected on-chip to the

IOM®-2 interface of the Timer Core. It is used for

connection to the following devices:

• PCM codec in the PCF5072

• Digital Audio Interface (DAI), used during type approval

• Terminal adaptor for data services

• External digital answering machine.

The physical transfer order on the IOM®-2 bus is 16-bit,

MSB first. The following signals are used:

• Serial data input SIYD

• Serial data output SOYD

• Serial shift clock SIYCLK

• Frame synchronization input SIYEN.

The DSP by default reads and writes the first 16-bit

timeslot of the IOM®-2 interface. This may be changed with

the appropriate software command to any 16-bit timeslot.

Input and output from/to the IOM®-2 bus is performed via

two FIFOs named audio input and audio output FIFO.

These FIFOs are implemented by firmware. Each FIFO is

able to store up to 297 16-bit samples.

BITS

NUMBER

OF BITS

DESCRIPTION

0 to 7

dummy bits (set to logic 1)

8 to 95

BN0 to BN87 in accordance

with

“GSM Rec. 05.02”

96 to 155

dummy bits (set to logic 1)

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