PCF5083HSLASH001SLASHF2 datasheet(101/136 Pages) PHILIPS

101 / 136 page

1996 Oct 29

101

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

Notes

1. R = read only; W = write only; R/W = read and write.

2. The flags of register IOMCON_REG should not be changed as long as the interface is enabled with

CLOCK_MODE = 0 to prevent an unpredictable behaviour of the interface.

reserved

−−

−

53 to 55

MONGAIN_REG

RF Bus: MON gain

56, 57

DAC0_REG

Gain DAC value 0

58, 59

DAC1_REG

Gain DAC value 1

5A, 5B

DACON_REG

Gain DAC power-up value

5C, 5D

DACOFF_REG

Gain DAC power-down value

reserved

−−

−

5E to 61

IMCIN_REG

IMC data in

IMCOUT_REG

IMC data out

MSB_REG

R/W

Gain Control Channel MSB Register

0: DAC0_REG bit 16

1: DAC1_REG bit 16

2: DACON_REG bit 16

3: DACOFF_REG bit 16

RFCTRL0_REG

RF bus control register 0

RFCTRL1_REG

RF bus control register 1

RFCTRL2_REG

RF bus control register 2

RFCTRL3_REG

RF bus control register 3

COMBINT_REG

R/W

Combined interrupt register; see Table 84

HIPRINT_REG

R/W

High priority interrupt register; see Table 85

HIPRMASK_REG

R/W

High priority interrupt mask register; see Table 86

SIINT_REG

Serial interface interrupt register; see Table 87

SIMASK_REG

R/W

Serial interface interrupt mask register; see Table 88

6C, 6D

IOMCON_REG(2)

R/W

IOM®-2 interface conﬁguration register; see Table 89

6E, 6F

ACON_REG

R/W

Audio Interface conﬁguration register; see Table 90

RXD_REG

RS232 data input register

TXD_REG

RS232 data output register

MON0_REG

R/W

IOM®-2 interface monitor 0 data register

MON1_REG

R/W

IOM®-2 interface monitor 1data register

CI0_REG

R/W

IOM®-2 interface C/I 0 data register

CI1_REG

R/W

IOM®-2 interface C/I 1 data register

IOMFLAG_REG

IOM®-2 interface interrupt ﬂag register; see Table 91

IOMCTRL_REG

R/W

IOM®-2 interface control register; see Table 92

IOMEN_REG

R/W

IOM®-2 interface interrupt enable register, see Table 93

PORTDATA_REG

R/W

Parallel port data register; see Table 94

PORTDDIR_REG

R/W

Parallel port data direction register; see Table 95

SYSCON_REG

R/W

System conﬁguration register; see Table 96

OFFSET

SIZE

R/W(1)

DESCRIPTION

PCF5083H/001/F2 数据表(PDF) 101 Page - NXP Semiconductors

PCF5083H/001/F2 数据表(HTML) 101 Page - NXP Semiconductors

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