PCF8548USLASH2 datasheet(18/40 Pages) PHILIPS

18 / 40 page

1999 Aug 16

Philips Semiconductors

Product speciﬁcation

× 102 pixels matrix LCD driver

PCF8548

12.2

Function set

12.2.1

POWER-DOWN (PD)

• All LCD outputs at VSS (display off)

• Bias generator and VLCD generator off

• Oscillator off (external clock possible)

• VLCD can be disconnected

• RAM contents not cleared (RAM data can be written)

• VLCD output is discharged to VSS.

12.2.2

When V = 0, the horizontal addressing is selected.

The data is written to the RAM as shown in Fig.4. When

V = 1, the vertical addressing is selected. The data is

written to the RAM as shown in Fig.5.

12.2.3

When H = 0 the commands ‘display control’, ‘set HV-gen

stages’, ‘set Y address’ and ‘set X address’ can be

performed. When H = 1 the other commands can be

executed. The commands ‘write data’ and ‘function set’

can be executed in both cases.

12.2.4

When MX = 0, the display RAM is written from left to right

(X = 0 is on the left side of the display, X = 100 is on the

right side of the display). When MX = 1 the display RAM is

written from right to left (X = 0 is on the right side of the

display, X = 100 is on the left side of the display).

Thus, if a horizontally mirroring of the display is desired the

RAM must first be rewritten.

12.2.5

When MY = 1, the display is mirrored vertically.

A change of this bit has an immediate effect on the display.

12.3

Display control

12.3.1

D AND E

The bits D and E select the display mode (see Table 2).

12.4

Display conﬁguration

12.4.1

TRS

Bit TRS enables the top row pad blocks to be mirrored.

This is used to enable flexibility in the wiring of the row

lines from the PCF8548 to the LCD cell (e.g. COG or TCP

wiring). When TRS = 0 rows 19 to 32 and rows 51 to 64

are organized as illustrated in Fig.22. When TRS = 1 rows

19 to 32 and rows 51 to 64 are mirrored and organized as

illustrated in Fig.23.

12.4.2

BRS

Bit BRS enables the bottom row pad blocks to be mirrored.

This is used to enable flexibility in the wiring of the row

lines from the PCF8548 to the LCD cell (e.g. COG or TCP

wiring). When BRS = 0 rows 0 to 18 and rows 33 to 50 are

organized as illustrated in Fig.22. When BRS = 1 rows

0 to 18 and rows 33 to 50 are mirrored and organized as

illustrated in Fig.23.

12.5

Set Y address of RAM

Y[3 : 0] defines the Y address vector address of the RAM.

Table 3

X and Y address ranges

Note

1. In bank 8 only the MSB is accessed.

CONTENT

ALLOWED X RANGE

bank 0 (display RAM)

0 to 101

bank 1 (display RAM)

0 to 101

bank 2 (display RAM)

0 to 101

bank 3 (display RAM)

0 to 101

bank 4 (display RAM)

0 to 101

bank 5 (display RAM)

0 to 101

bank 6 (display RAM)

0 to 101

bank 7 (display RAM)

0 to 101

bank 8 (display RAM); note 1

0 to 101

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