PCF8548USLASH2 datasheet(24/40 Pages) PHILIPS

24 / 40 page

1999 Aug 16

Philips Semiconductors

Product speciﬁcation

× 102 pixels matrix LCD driver

PCF8548

16 AC CHARACTERISTICS

VDD1 = 1.9 to 5.5 V; VDD2 and VDD3 = 2.4 to 4.5 V; VSS1 and VSS2 =0V; VLCD = 4.5 to 9 V; Tamb = −40 to +85 °C;

unless otherwise speciﬁed.

Notes

2. RES may be LOW before VDD1 goes HIGH.

3. If tW(RES) is longer than 3 ns (typical) a reset may be generated.

4. All timing values are valid within the operating supply voltage and ambient temperature ranges and are referenced

to VIL and VIH with an input voltage swing of VSS to VDD.

5. The rise and fall times specified here refer to the driver device (i.e. not PCF8548) and are part of the general fast

I2C-bus specification. When PCF8548 asserts an acknowledge on SDA, the minimum fall time is 10 ns.

Cb = capacitive load per bus line.

6. The device inputs SDA and SCL are filtered and will reject spikes on the bus lines of width <tSW(max).

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

fOSC

oscillator frequency

VDD1 = 2.8 V;

Tamb = −20 to +70 °C

kHz

fclk(ext)

external clock frequency

100

kHz

fframe

frame frequency

fOSC or fclk(ext) = 38 kHz;

note 1

−

tVHRL

VDD1 to RES LOW

see Fig.17 and note 2

−

µs

tW(RES)

RES LOW pulse width

see Fig.17 and note 3

100

−−

I2C-bus timing characteristics; see note 4

fSCLK

SCL clock frequency

−

400

kHz

tSCLL

SCL clock LOW period

1.3

−−µs

tSCLH

SCL clock HIGH period

0.6

−−µs

tSU;DAT

data set-up time

100

−−

tHD;DAT

data hold time

−

0.9

µs

SCL and SDA rise time

note 5

20 + 0.1Cb

−

300

SCL and SDA fall time

note 5

20 + 0.1Cb

−

300

tf(SDA)(ro)

SDA fall time for read out

VDD1 = <3.6 V

20 + 0.1Cb

−

1000

capacitive load represented by each

bus line

−−

400

tSU;STA

set-up time for a repeated START

condition

0.6

−−µs

tHD;STA

START condition hold time

0.6

−−µs

tSU;STO

set-up time for STOP condition

0.6

−−µs

tSW

tolerable spike width on bus

note 6

−−

tBUF

bus free time between a STOP and

START condition

1.3

−−µs

frame

clk ext

()

520

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