PCF8549USLASH2SLASHF1 datasheet(5/36 Pages) PHILIPS

5 / 36 page

1997 Nov 21

Philips Semiconductors

Product speciﬁcation

× 102 pixels matrix LCD driver

PCF8549

T1, T2, T3, T4, T5, T6 AND T7: TEST PADS

T1, T3, T4, T5, T6 and T7 must be connected to VSS1, T2

is to be left open. Not accessible to user.

SDA/SDA_OUT: I2CDATA LINES

Output and input are separated. If both pads are

connected together they behave like a standard I2C pad.

SCL: I2C CLOCK SIGNAL

Input for the I2C-bus clock signal.

SA0: SLAVE ADDRESS

With the SA0 pin two different slave addresses can be

selected. That allows to connect two PCF8549 LCD

drivers to the same I2C-bus.

OSC: OSCILLATOR

When the on-chip oscillator is used this input must be

connected to VDD1. An external clock signal, if used, is

connected to this input.

RES: RESET

This signal will reset the device. Signal is active low.

FUNCTIONAL DESCRIPTION

Block diagram functions

OSCILLATOR

The on-chip oscillator provides the clock signal for the

display system. No external components are required and

the OSC input must be connected to VDD1. An external

clock signal, if used, is connected to this input.

I2CINTERFACE

The I2C interface receives and executes the commands

sent via the I2C-bus. It also receives RAM-data and sends

them to the RAM. During read access the 8-bit parallel

data or the status register content is converted to a serial

data stream and output via the I2C-bus.

DISPLAY CONTROL LOGIC

The display control logic generates the control signals to

read out the RAM via the 101 bit parallel port. It also

generates the control signals for the row, and

column drivers.

DISPLAY DATA RAM (DDRAM)

The PCF8549 contains a 65

× 102 bit static RAM which

stores the display data. The RAM is divided into 8 banks of

102 bytes and one bank of 102 bits

((8

× 8+1) × 102 bits). During RAM access, data is

transferred to the RAM via the I2C interface. There is a

direct correspondence between X-address and column

output number.

TIMING GENERATOR

The timing generator produces the various signals

required to drive the internal circuitry. Internal chip

operation is not disturbed by operations on the I2C-bus.

LCD ROW AND COLUMN DRIVERS

The PCF8549 contains 65 row and 102 column drivers,

which connect the appropriate LCD bias voltages to the

display in accordance with the data to be displayed.

Figure 2 shows typical waveforms. Unused outputs should

be left unconnected.

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