PCF8549USLASH2SLASHF1 datasheet(8/36 Pages) PHILIPS

8 / 36 page

1997 Nov 21

Philips Semiconductors

Product speciﬁcation

× 102 pixels matrix LCD driver

PCF8549

Addressing

The Display data RAM of the PCF8549 is accessed as

indicated in Figs 3, 4, 4, 6 and 7. The display RAM has a

matrix of 65

× 102 bits. The columns are addressed by the

address pointer. The address ranges are:

X 0 to 101 (1100101b) and Y 0 to 8 (1000b). Addresses

outside these ranges are not allowed. In vertical

addressing mode (V = 1) the Y address increments (see

Fig.7) after each byte. After the last Y address (Y = 8)

Y wraps around to 0 and X increments to address the next

column. In horizontal addressing mode (V = 0) the

X address increments (see Fig.6) after each byte. After the

last X address (X = 101) X wraps around to

0 and Y increments to address the next row. After the very

last address (X = 101 and Y = 8) the address pointers

wrap around to address (X = 0 and Y = 0).

The MX bit allows a horizontal mirroring: When MX = 1,

the X address space is mirrored: The addressX=0 is

then located at the right side (column 101) of the display

(see Fig.4). When MX = 0 the mirroring is disabled and the

address X = 0 is located at the left side (column 0) of the

display (see Fig.4).

If the RM-bit (read-modify-write mode) is set, the address

is only incremented after a write, otherwise the address is

incremented after both read and write access to the

display data RAM.

PCF8549U/2/F1 数据表(PDF) 8 Page - NXP Semiconductors